39use ieee.std_logic_1164.
all;
40use ieee.numeric_std.
all;
78 subtype df_byte3 is integer range 31 downto 24;
79 subtype df_byte2 is integer range 23 downto 16;
83 subtype df_word1 is integer range 31 downto 16;
140 report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH"
155 ADDRB => R_REGS.addr_l,
174 ADDRB => R_REGS.addr_l,
193 ADDRB => R_REGS.addr_l,
212 ADDRB => R_REGS.addr_l,
231 ADDRB => R_REGS.addr_l,
241 if rising_edge(CLK) then
249 end process proc_regs;
259 variable iaddr_w : slbit := '0';
260 variable iaddr_l : slv(l_range) := (others=>'0');
261 variable iaddr_t : slv(t_range) := (others=>'0');
263 variable itagok : slbit := '0';
264 variable ivalok : slbit := '0';
266 variable icmem_tag_cea : slbit := '0';
267 variable icmem_tag_ceb : slbit := '0';
268 variable icmem_tag_wea : slbit := '0';
269 variable icmem_tag_web : slbit := '0';
270 variable icmem_tag_dib : slv(t_range) := (others=>'0');
271 variable icmem_dat_cea : slbit := '0';
272 variable icmem_dat_ceb : slbit := '0';
273 variable icmem_dat_wea : slv4 := "0000";
274 variable icmem_dat_web : slv4 := "0000";
275 variable icmem_val_doa : slv4 := "0000";
276 variable icmem_dat_doa : slv32 := (others=>'0');
277 variable icmem_val_dib : slv4 := "0000";
278 variable icmem_dat_dib : slv32 := (others=>'0');
280 variable iackr : slbit := '0';
281 variable iackw : slbit := '0';
282 variable iosel : slv2 := "11";
283 variable istat : dm_stat_ca_type := dm_stat_ca_init;
285 variable imem_reqr : slbit := '0';
286 variable imem_reqw : slbit := '0';
287 variable imem_be : slv4 := "0000";
298 icmem_tag_cea := '0';
299 icmem_tag_ceb := '0';
300 icmem_tag_wea := '0';
301 icmem_tag_web := '0';
302 icmem_tag_dib := r.addr_t;
303 icmem_dat_cea := '0';
304 icmem_dat_ceb := '0';
305 icmem_dat_wea := "0000";
306 icmem_dat_web := "0000";
307 icmem_val_dib := "0000";
324 if (icmem_val_doa and r.be) = r.be then
334 istat := dm_stat_ca_init;
346 icmem_tag_cea := '1';
347 icmem_dat_cea := '1';
348 if iaddr_w = '0' then
349 n.be(1 downto 0) := EM_MREQ.be;
351 n.be(3 downto 2) := EM_MREQ.be;
360 icmem_tag_wea := '1';
361 icmem_dat_wea := n.be;
367 iosel := '0' & r.addr_w;
370 if FMISS='0' and itagok='1' and ivalok='1' then
390 iosel := '1' & r.addr_w;
391 icmem_tag_web := '1';
392 icmem_tag_dib := r.addr_t;
393 icmem_val_dib := "1111";
395 icmem_dat_web := "1111";
399 icmem_tag_ceb := '1';
400 icmem_dat_ceb := '1';
406 icmem_dat_dib := icmem_dat_doa;
411 icmem_dat_ceb := '1';
412 icmem_dat_web := not r.be;
413 icmem_val_dib := "0000";
426 icmem_tag_ceb := '1';
427 icmem_tag_web := '1';
428 icmem_dat_ceb := '1';
429 icmem_dat_web := "1111";
430 icmem_val_dib := icmem_val_doa;
480 MEM_REQ <= imem_reqr or imem_reqw;
486 end process proc_next;
slv9 :=( others => '0') CMEM_DIB_2
integer range 31 downto 16 df_word1
integer range 31 downto 24 df_byte3
slv9 :=( others => '0') CMEM_DOA_2
integer range 7 downto 0 df_byte0
integer range 15 downto 8 df_byte1
slv9 :=( others => '0') CMEM_DIB_1
integer range TWIDTH- 1 downto 0 t_range
slv( t_range ) :=( others => '0') CMEM_TAG_DOA
integer range 22- 1 downto 22- TWIDTH af_tag
slbit := '0' CMEM_TAG_WEB
(s_idle,s_read,s_rmiss,s_write) state_type
slv9 :=( others => '0') CMEM_DIB_0
slbit := '0' CMEM_TAG_CEB
slbit := '0' CMEM_DAT_CEA
slv9 :=( others => '0') CMEM_DIA_1
slv9 :=( others => '0') CMEM_DOA_0
integer range 23 downto 16 df_byte2
slbit := '0' CMEM_DAT_CEB
regs_type := regs_init R_REGS
integer range 15 downto 0 df_word0
regs_type :=( s_idle, '0', slv( to_unsigned( 0, lwidth) ), slv( to_unsigned( 0, TWIDTH) ),( others => '0'),( others => '0')) regs_init
slbit := '0' CMEM_TAG_CEA
slv4 := "0000" CMEM_DAT_WEA
slv9 :=( others => '0') CMEM_DOA_3
slv9 :=( others => '0') CMEM_DIA_0
slv9 :=( others => '0') CMEM_DIB_3
slv9 :=( others => '0') CMEM_DOA_1
slv9 :=( others => '0') CMEM_DIA_3
integer range lwidth- 1 downto 0 l_range
slv4 := "0000" CMEM_DAT_WEB
slv9 :=( others => '0') CMEM_DIA_2
integer range 22- TWIDTH- 1 downto 2 af_line
positive := 22- 2- TWIDTH lwidth
slbit := '0' CMEM_TAG_WEA
slv( t_range ) :=( others => '0') CMEM_TAG_DIB
out DM_STAT_CA dm_stat_ca_type
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 1 downto 0) slv2