w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_cache.vhd
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1-- $Id: pdp11_cache.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_cache - syn
7-- Description: pdp11: cache
8--
9-- Dependencies: memlib/ram_2swsr_rfirst_gen
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
13--
14-- Synthesis results
15-- clw = cache line width (tag+data)
16-- eff = efficiency (fraction of used BRAM colums)
17-- - 2016-03-22 (r750) with viv 2015.4 for xc7a100t-1
18-- TWIDTH size flop lutl lutm RAMB36 RAMB18 bram clw eff
19-- 9 8k 43 106 0 0 5 2.5 45 100%
20-- 8 16k 43 109 0 5 0 5.0 44 97%
21-- 7 32k 43 107 0 10 4 12.0 43 89%
22-- 6 64k 43 106 0 19 4 21.0 42 100%
23-- 5 128k 58! 106 0 41 0 41.0 41 100%
24--
25-- Revision History:
26-- Date Rev Version Comment
27-- 2018-10-06 1053 1.2 drop CHIT, use DM_STAT_CA, detailed monitoring
28-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
29-- 2016-03-22 751 1.1 now configurable size (8,16,32,64,128 kB)
30-- 2011-11-18 427 1.0.3 now numeric_std clean
31-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
32-- factor invariants out of if's; fix tag rmiss logic
33-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
34-- recode, ghdl doesn't like partial vector port maps
35-- 2008-02-16 116 1.0 Initial version
36------------------------------------------------------------------------------
37
38library ieee;
39use ieee.std_logic_1164.all;
40use ieee.numeric_std.all;
41
42use work.slvtypes.all;
43use work.memlib.all;
44use work.pdp11.all;
45
46entity pdp11_cache is -- cache
47 generic (
48 TWIDTH : positive := 9); -- tag width (5 to 9)
49 port (
50 CLK : in slbit; -- clock
51 GRESET : in slbit; -- general reset
52 EM_MREQ : in em_mreq_type; -- em request
53 EM_SRES : out em_sres_type; -- em response
54 FMISS : in slbit; -- force miss
55 MEM_REQ : out slbit; -- memory: request
56 MEM_WE : out slbit; -- memory: write enable
57 MEM_BUSY : in slbit; -- memory: controller busy
58 MEM_ACK_R : in slbit; -- memory: acknowledge read
59 MEM_ADDR : out slv20; -- memory: address
60 MEM_BE : out slv4; -- memory: byte enable
61 MEM_DI : out slv32; -- memory: data in (memory view)
62 MEM_DO : in slv32; -- memory: data out (memory view)
63 DM_STAT_CA : out dm_stat_ca_type -- debug and monitor status - cache
64 );
65end pdp11_cache;
66
67
68architecture syn of pdp11_cache is
69
70 constant lwidth: positive := 22-2-TWIDTH; -- line address width
71
72 subtype t_range is integer range TWIDTH-1 downto 0; -- tag value regs
73 subtype l_range is integer range lwidth-1 downto 0; -- line addr regs
74
75 subtype af_tag is integer range 22-1 downto 22-TWIDTH; -- tag address
76 subtype af_line is integer range 22-TWIDTH-1 downto 2; -- line address
77
78 subtype df_byte3 is integer range 31 downto 24;
79 subtype df_byte2 is integer range 23 downto 16;
80 subtype df_byte1 is integer range 15 downto 8;
81 subtype df_byte0 is integer range 7 downto 0;
82
83 subtype df_word1 is integer range 31 downto 16;
84 subtype df_word0 is integer range 15 downto 0;
85
86 type state_type is (
87 s_idle, -- s_idle: wait for req
88 s_read, -- s_read: read cycle
89 s_rmiss, -- s_rmiss: read miss
90 s_write -- s_write: write cycle
91 );
92
93 type regs_type is record
94 state : state_type; -- state
95 addr_w : slbit; -- address - word select
96 addr_l : slv(l_range); -- address - cache line address
97 addr_t : slv(t_range); -- address - cache tag part
98 be : slv4; -- byte enables (at 4 byte level)
99 di : slv16; -- data
100 end record regs_type;
101
102 constant regs_init : regs_type := (
103 s_idle, -- state
104 '0', -- addr_w
105 slv(to_unsigned(0,lwidth)), -- addr_l
106 slv(to_unsigned(0,TWIDTH)), -- addr_t
107 (others=>'0'), -- be
108 (others=>'0') -- di
109 );
110
112 signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
113
114 signal CMEM_TAG_CEA : slbit := '0';
115 signal CMEM_TAG_CEB : slbit := '0';
116 signal CMEM_TAG_WEA : slbit := '0';
117 signal CMEM_TAG_WEB : slbit := '0';
118 signal CMEM_TAG_DIB : slv(t_range) := (others=>'0');
119 signal CMEM_TAG_DOA : slv(t_range) := (others=>'0');
120 signal CMEM_DAT_CEA : slbit := '0';
121 signal CMEM_DAT_CEB : slbit := '0';
122 signal CMEM_DAT_WEA : slv4 := "0000";
123 signal CMEM_DAT_WEB : slv4 := "0000";
124 signal CMEM_DIA_0 : slv9 := (others=>'0');
125 signal CMEM_DIA_1 : slv9 := (others=>'0');
126 signal CMEM_DIA_2 : slv9 := (others=>'0');
127 signal CMEM_DIA_3 : slv9 := (others=>'0');
128 signal CMEM_DIB_0 : slv9 := (others=>'0');
129 signal CMEM_DIB_1 : slv9 := (others=>'0');
130 signal CMEM_DIB_2 : slv9 := (others=>'0');
131 signal CMEM_DIB_3 : slv9 := (others=>'0');
132 signal CMEM_DOA_0 : slv9 := (others=>'0');
133 signal CMEM_DOA_1 : slv9 := (others=>'0');
134 signal CMEM_DOA_2 : slv9 := (others=>'0');
135 signal CMEM_DOA_3 : slv9 := (others=>'0');
136
137begin
138
139 assert TWIDTH>=5 and TWIDTH<=9
140 report "assert(TWIDTH>=5 and TWIDTH<=9): unsupported TWIDTH"
141 severity failure;
142
143 CMEM_TAG : ram_2swsr_rfirst_gen
144 generic map (
145 AWIDTH => lwidth,
146 DWIDTH => twidth)
147 port map (
148 CLKA => CLK,
149 CLKB => CLK,
150 ENA => CMEM_TAG_CEA,
151 ENB => CMEM_TAG_CEB,
152 WEA => CMEM_TAG_WEA,
153 WEB => CMEM_TAG_WEB,
154 ADDRA => EM_MREQ.addr(af_line),
155 ADDRB => R_REGS.addr_l,
156 DIA => EM_MREQ.addr(af_tag),
157 DIB => CMEM_TAG_DIB,
158 DOA => CMEM_TAG_DOA,
159 DOB => open
160 );
161
162 CMEM_DAT0 : ram_2swsr_rfirst_gen
163 generic map (
164 AWIDTH => lwidth,
165 DWIDTH => 9)
166 port map (
167 CLKA => CLK,
168 CLKB => CLK,
169 ENA => CMEM_DAT_CEA,
170 ENB => CMEM_DAT_CEB,
171 WEA => CMEM_DAT_WEA(0),
172 WEB => CMEM_DAT_WEB(0),
173 ADDRA => EM_MREQ.addr(af_line),
174 ADDRB => R_REGS.addr_l,
175 DIA => CMEM_DIA_0,
176 DIB => CMEM_DIB_0,
177 DOA => CMEM_DOA_0,
178 DOB => open
179 );
180
181 CMEM_DAT1 : ram_2swsr_rfirst_gen
182 generic map (
183 AWIDTH => lwidth,
184 DWIDTH => 9)
185 port map (
186 CLKA => CLK,
187 CLKB => CLK,
188 ENA => CMEM_DAT_CEA,
189 ENB => CMEM_DAT_CEB,
190 WEA => CMEM_DAT_WEA(1),
191 WEB => CMEM_DAT_WEB(1),
192 ADDRA => EM_MREQ.addr(af_line),
193 ADDRB => R_REGS.addr_l,
194 DIA => CMEM_DIA_1,
195 DIB => CMEM_DIB_1,
196 DOA => CMEM_DOA_1,
197 DOB => open
198 );
199
200 CMEM_DAT2 : ram_2swsr_rfirst_gen
201 generic map (
202 AWIDTH => lwidth,
203 DWIDTH => 9)
204 port map (
205 CLKA => CLK,
206 CLKB => CLK,
207 ENA => CMEM_DAT_CEA,
208 ENB => CMEM_DAT_CEB,
209 WEA => CMEM_DAT_WEA(2),
210 WEB => CMEM_DAT_WEB(2),
211 ADDRA => EM_MREQ.addr(af_line),
212 ADDRB => R_REGS.addr_l,
213 DIA => CMEM_DIA_2,
214 DIB => CMEM_DIB_2,
215 DOA => CMEM_DOA_2,
216 DOB => open
217 );
218
219 CMEM_DAT3 : ram_2swsr_rfirst_gen
220 generic map (
221 AWIDTH => lwidth,
222 DWIDTH => 9)
223 port map (
224 CLKA => CLK,
225 CLKB => CLK,
226 ENA => CMEM_DAT_CEA,
227 ENB => CMEM_DAT_CEB,
228 WEA => CMEM_DAT_WEA(3),
229 WEB => CMEM_DAT_WEB(3),
230 ADDRA => EM_MREQ.addr(af_line),
231 ADDRB => R_REGS.addr_l,
232 DIA => CMEM_DIA_3,
233 DIB => CMEM_DIB_3,
234 DOA => CMEM_DOA_3,
235 DOB => open
236 );
237
238 proc_regs: process (CLK)
239 begin
240
241 if rising_edge(CLK) then
242 if GRESET = '1' then
243 R_REGS <= regs_init;
244 else
245 R_REGS <= N_REGS;
246 end if;
247 end if;
248
249 end process proc_regs;
250
251 proc_next: process (R_REGS, EM_MREQ, FMISS,
255
256 variable r : regs_type := regs_init;
257 variable n : regs_type := regs_init;
258
259 variable iaddr_w : slbit := '0';
260 variable iaddr_l : slv(l_range) := (others=>'0');
261 variable iaddr_t : slv(t_range) := (others=>'0');
262
263 variable itagok : slbit := '0';
264 variable ivalok : slbit := '0';
265
266 variable icmem_tag_cea : slbit := '0';
267 variable icmem_tag_ceb : slbit := '0';
268 variable icmem_tag_wea : slbit := '0';
269 variable icmem_tag_web : slbit := '0';
270 variable icmem_tag_dib : slv(t_range) := (others=>'0');
271 variable icmem_dat_cea : slbit := '0';
272 variable icmem_dat_ceb : slbit := '0';
273 variable icmem_dat_wea : slv4 := "0000";
274 variable icmem_dat_web : slv4 := "0000";
275 variable icmem_val_doa : slv4 := "0000";
276 variable icmem_dat_doa : slv32 := (others=>'0');
277 variable icmem_val_dib : slv4 := "0000";
278 variable icmem_dat_dib : slv32 := (others=>'0');
279
280 variable iackr : slbit := '0';
281 variable iackw : slbit := '0';
282 variable iosel : slv2 := "11";
283 variable istat : dm_stat_ca_type := dm_stat_ca_init;
284
285 variable imem_reqr : slbit := '0';
286 variable imem_reqw : slbit := '0';
287 variable imem_be : slv4 := "0000";
288
289 begin
290
291 r := R_REGS;
292 n := R_REGS;
293
294 iaddr_w := EM_MREQ.addr(1); -- get word select
295 iaddr_l := EM_MREQ.addr(af_line); -- get cache line addr
296 iaddr_t := EM_MREQ.addr(af_tag); -- get cache tag part
297
298 icmem_tag_cea := '0';
299 icmem_tag_ceb := '0';
300 icmem_tag_wea := '0';
301 icmem_tag_web := '0';
302 icmem_tag_dib := r.addr_t; -- default, local define whenver used
303 icmem_dat_cea := '0';
304 icmem_dat_ceb := '0';
305 icmem_dat_wea := "0000";
306 icmem_dat_web := "0000";
307 icmem_val_dib := "0000";
308 icmem_dat_dib := MEM_DO; -- default, local define whenver used
309
310 icmem_val_doa(0) := CMEM_DOA_0(8);
311 icmem_dat_doa(df_byte0) := CMEM_DOA_0(df_byte0);
312 icmem_val_doa(1) := CMEM_DOA_1(8);
313 icmem_dat_doa(df_byte1) := CMEM_DOA_1(df_byte0);
314 icmem_val_doa(2) := CMEM_DOA_2(8);
315 icmem_dat_doa(df_byte2) := CMEM_DOA_2(df_byte0);
316 icmem_val_doa(3) := CMEM_DOA_3(8);
317 icmem_dat_doa(df_byte3) := CMEM_DOA_3(df_byte0);
318
319 itagok := '0';
320 if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
321 itagok := '1';
322 end if;
323 ivalok := '0';
324 if (icmem_val_doa and r.be) = r.be then
325 ivalok := '1';
326 end if;
327
328 iackr := '0';
329 iackw := '0';
330 iosel := "11"; -- default to ext. mem data
331 -- this prevents U's from cache bram's
332 -- to propagate to dout in beginning...
333
334 istat := dm_stat_ca_init;
335
336 imem_reqr := '0';
337 imem_reqw := '0';
338 imem_be := r.be;
339
340 case r.state is
341 when s_idle => -- s_idle: wait for req
342 n.addr_w := iaddr_w; -- capture address: word select
343 n.addr_l := iaddr_l; -- capture address: cache line addr
344 n.addr_t := iaddr_t; -- capture address: cache tag part
345 n.be := "0000";
346 icmem_tag_cea := '1'; -- access cache tag port A
347 icmem_dat_cea := '1'; -- access cache data port A
348 if iaddr_w = '0' then -- capture byte enables at 4 byte lvl
349 n.be(1 downto 0) := EM_MREQ.be;
350 else
351 n.be(3 downto 2) := EM_MREQ.be;
352 end if;
353 n.di := EM_MREQ.din; -- capture data
354
355 if EM_MREQ.req = '1' then -- if access requested
356 if EM_MREQ.we = '0' then -- if READ requested
357 n.state := s_read; -- next: read
358
359 else -- if WRITE requested
360 icmem_tag_wea := '1'; -- write tag
361 icmem_dat_wea := n.be; -- write cache data
362 n.state := s_write; -- next: write
363 end if;
364 end if;
365
366 when s_read => -- s_read: read cycle
367 iosel := '0' & r.addr_w; -- output select: cache
368 imem_be := "1111"; -- mem read: all 4 bytes
369 if EM_MREQ.cancel = '0' then
370 if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit
371 istat.rd := '1'; -- moni read request (hit)
372 iackr := '1'; -- signal read acknowledge
373 istat.rdhit := '1'; -- moni read hit
374 n.state := s_idle; -- next: back to idle
375 else -- read miss
376 if MEM_BUSY = '0' then -- if mem not busy
377 istat.rd := '1'; -- moni read request (!hit & !wait)
378 imem_reqr :='1'; -- request mem read
379 istat.rdmem := '1'; -- moni mem read
380 n.state := s_rmiss; -- next: rmiss, wait for mem data
381 else -- else mem busy
382 istat.wrwait := '1'; -- moni mem busy
383 end if;
384 end if;
385 else
386 n.state := s_idle; -- next: back to idle
387 end if;
388
389 when s_rmiss => -- s_rmiss: read cycle
390 iosel := '1' & r.addr_w; -- output select: memory
391 icmem_tag_web := '1'; -- cache update: write tag
392 icmem_tag_dib := r.addr_t; -- cache update: new tag
393 icmem_val_dib := "1111"; -- cache update: all valid
394 icmem_dat_dib := MEM_DO; -- cache update: data from mem
395 icmem_dat_web := "1111"; -- cache update: write all 4 bytes
396 istat.rdwait := '1'; -- moni read wait
397 if MEM_ACK_R = '1' then -- mem data valid
398 iackr := '1'; -- signal read acknowledge
399 icmem_tag_ceb := '1'; -- access cache tag port B
400 icmem_dat_ceb := '1'; -- access cache data port B
401 n.state := s_idle; -- next: back to idle
402 end if;
403
404 when s_write => -- s_write: write cycle
405 icmem_tag_dib := CMEM_TAG_DOA; -- cache restore: last state
406 icmem_dat_dib := icmem_dat_doa; -- cache restore: last state
407 if EM_MREQ.cancel = '0' then -- request ok
408 if MEM_BUSY = '0' then -- if mem not busy
409 istat.wr := '1'; -- moni write request
410 if itagok = '0' then -- if write tag miss
411 icmem_dat_ceb := '1'; -- access cache (invalidate)
412 icmem_dat_web := not r.be; -- write missed bytes
413 icmem_val_dib := "0000"; -- invalidate missed bytes
414 else
415 istat.wrhit := '1'; -- moni write hit
416 end if;
417 imem_reqw := '1'; -- write back to main memory
418 istat.wrmem := '1'; -- moni mem write
419 iackw := '1'; -- and done
420 n.state := s_idle; -- next: back to idle
421 else -- else mem busy
422 istat.wrwait := '1'; -- moni mem busy
423 end if;
424
425 else -- request canceled -> restore
426 icmem_tag_ceb := '1'; -- access cache line
427 icmem_tag_web := '1'; -- write tag
428 icmem_dat_ceb := '1'; -- access cache line
429 icmem_dat_web := "1111"; -- restore cache line
430 icmem_val_dib := icmem_val_doa; -- cache restore: last state
431 n.state := s_idle; -- next: back to idle
432 end if;
433
434 when others => null;
435 end case;
436
437 N_REGS <= n;
438
439 CMEM_TAG_CEA <= icmem_tag_cea;
440 CMEM_TAG_CEB <= icmem_tag_ceb;
441 CMEM_TAG_WEA <= icmem_tag_wea;
442 CMEM_TAG_WEB <= icmem_tag_web;
443 CMEM_TAG_DIB <= icmem_tag_dib;
444 CMEM_DAT_CEA <= icmem_dat_cea;
445 CMEM_DAT_CEB <= icmem_dat_ceb;
446 CMEM_DAT_WEA <= icmem_dat_wea;
447 CMEM_DAT_WEB <= icmem_dat_web;
448
449 CMEM_DIA_0(8) <= '1';
451 CMEM_DIA_1(8) <= '1';
453 CMEM_DIA_2(8) <= '1';
455 CMEM_DIA_3(8) <= '1';
457
458 CMEM_DIB_0(8) <= icmem_val_dib(0);
459 CMEM_DIB_0(df_byte0) <= icmem_dat_dib(df_byte0);
460 CMEM_DIB_1(8) <= icmem_val_dib(1);
461 CMEM_DIB_1(df_byte0) <= icmem_dat_dib(df_byte1);
462 CMEM_DIB_2(8) <= icmem_val_dib(2);
463 CMEM_DIB_2(df_byte0) <= icmem_dat_dib(df_byte2);
464 CMEM_DIB_3(8) <= icmem_val_dib(3);
465 CMEM_DIB_3(df_byte0) <= icmem_dat_dib(df_byte3);
466
467 EM_SRES <= em_sres_init;
468 EM_SRES.ack_r <= iackr;
469 EM_SRES.ack_w <= iackw;
470 case iosel is
471 when "00" => EM_SRES.dout <= icmem_dat_doa(df_word0);
472 when "01" => EM_SRES.dout <= icmem_dat_doa(df_word1);
473 when "10" => EM_SRES.dout <= MEM_DO(df_word0);
474 when "11" => EM_SRES.dout <= MEM_DO(df_word1);
475 when others => null;
476 end case;
477
478 DM_STAT_CA <= istat;
479
480 MEM_REQ <= imem_reqr or imem_reqw;
481 MEM_WE <= imem_reqw;
482 MEM_ADDR <= r.addr_t & r.addr_l;
483 MEM_BE <= imem_be;
484 MEM_DI <= r.di & r.di;
485
486 end process proc_next;
487
488end syn;
slv9 :=( others => '0') CMEM_DIB_2
integer range 31 downto 16 df_word1
Definition: pdp11_cache.vhd:83
integer range 31 downto 24 df_byte3
Definition: pdp11_cache.vhd:78
slv9 :=( others => '0') CMEM_DOA_2
integer range 7 downto 0 df_byte0
Definition: pdp11_cache.vhd:81
integer range 15 downto 8 df_byte1
Definition: pdp11_cache.vhd:80
slv9 :=( others => '0') CMEM_DIB_1
integer range TWIDTH- 1 downto 0 t_range
Definition: pdp11_cache.vhd:72
slv( t_range ) :=( others => '0') CMEM_TAG_DOA
integer range 22- 1 downto 22- TWIDTH af_tag
Definition: pdp11_cache.vhd:75
slbit := '0' CMEM_TAG_WEB
(s_idle,s_read,s_rmiss,s_write) state_type
Definition: pdp11_cache.vhd:86
slv9 :=( others => '0') CMEM_DIB_0
slbit := '0' CMEM_TAG_CEB
slbit := '0' CMEM_DAT_CEA
slv9 :=( others => '0') CMEM_DIA_1
slv9 :=( others => '0') CMEM_DOA_0
integer range 23 downto 16 df_byte2
Definition: pdp11_cache.vhd:79
slbit := '0' CMEM_DAT_CEB
regs_type := regs_init R_REGS
integer range 15 downto 0 df_word0
Definition: pdp11_cache.vhd:84
regs_type :=( s_idle, '0', slv( to_unsigned( 0, lwidth) ), slv( to_unsigned( 0, TWIDTH) ),( others => '0'),( others => '0')) regs_init
slbit := '0' CMEM_TAG_CEA
regs_type N_REGS
slv4 := "0000" CMEM_DAT_WEA
slv9 :=( others => '0') CMEM_DOA_3
slv9 :=( others => '0') CMEM_DIA_0
slv9 :=( others => '0') CMEM_DIB_3
slv9 :=( others => '0') CMEM_DOA_1
slv9 :=( others => '0') CMEM_DIA_3
integer range lwidth- 1 downto 0 l_range
Definition: pdp11_cache.vhd:73
slv4 := "0000" CMEM_DAT_WEB
slv9 :=( others => '0') CMEM_DIA_2
integer range 22- TWIDTH- 1 downto 2 af_line
Definition: pdp11_cache.vhd:76
positive := 22- 2- TWIDTH lwidth
Definition: pdp11_cache.vhd:70
slbit := '0' CMEM_TAG_WEA
slv( t_range ) :=( others => '0') CMEM_TAG_DIB
in MEM_BUSY slbit
Definition: pdp11_cache.vhd:57
out MEM_DI slv32
Definition: pdp11_cache.vhd:61
in EM_MREQ em_mreq_type
Definition: pdp11_cache.vhd:52
out DM_STAT_CA dm_stat_ca_type
Definition: pdp11_cache.vhd:64
out MEM_BE slv4
Definition: pdp11_cache.vhd:60
in GRESET slbit
Definition: pdp11_cache.vhd:51
in CLK slbit
Definition: pdp11_cache.vhd:50
out MEM_REQ slbit
Definition: pdp11_cache.vhd:55
in MEM_ACK_R slbit
Definition: pdp11_cache.vhd:58
out MEM_ADDR slv20
Definition: pdp11_cache.vhd:59
in MEM_DO slv32
Definition: pdp11_cache.vhd:62
out MEM_WE slbit
Definition: pdp11_cache.vhd:56
TWIDTH positive := 9
Definition: pdp11_cache.vhd:48
in FMISS slbit
Definition: pdp11_cache.vhd:54
out EM_SRES em_sres_type
Definition: pdp11_cache.vhd:53
Definition: pdp11.vhd:123
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31