w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_dmcmon.vhd
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1-- $Id: pdp11_dmcmon.vhd 1330 2022-12-16 17:52:40Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_dmcmon- syn
7-- Description: pdp11: debug&moni: cpu monitor
8--
9-- Dependencies: memlib/ram_2swsr_rfirst_gen
10-- memlib/ram_1swar_1ar_gen
11-- Test bench: -
12--
13-- Target Devices: generic
14-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
15--
16-- Synthesized (xst):
17-- Date Rev ise Target flop lutl lutm slic t peri
18-- 2015-08-02 707 14.7 131013 xc6slx16-2 213 233 16 151 s 5.9
19--
20-- Revision History: -
21-- Date Rev Version Comment
22-- 2022-12-12 1330 2.0.3 dm_stat_se_type: rename vfetch -> vstart
23-- 2022-10-25 1309 2.0.2 rename _gpr -> _gr
24-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
25-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
26-- 2015-08-03 709 1.0 Initial version
27-- 2015-07-05 697 0.1 First draft
28------------------------------------------------------------------------------
29--
30-- rbus registers:
31--
32-- Addr Bits Name r/w/f Function
33-- 000 cntl r/w/f Control register
34-- 05 mwsup r/w/- mem wait suppress
35-- 04 imode r/w/- instruction mode
36-- 03 wstop r/w/- stop on wrap
37-- 02:00 func 0/-/f change run status if != noop
38-- 0xx noop
39-- 100 sto stop
40-- 101 sta start and latch all options
41-- 110 sus suspend (noop if not started)
42-- 111 res resume (noop if not started)
43-- 001 stat r/-/- Status register
44-- 15:13 bsize r/-/- buffer size (AWIDTH-8)
45-- 12:09 malcnt r/-/- valid entries in memory access log
46-- 08 snum r/-/- snum support
47-- 02 wrap r/-/- line address wrapped (cleared on start)
48-- 01 susp r/-/- suspended
49-- 00 run r/-/- running (can be suspended)
50-- 010 addr r/w/- Address register (writable when stopped)
51-- *:04 laddr r/w/- line address
52-- 03:00 waddr r/w/- word address (0000 to 1000)
53-- 011 data r/w/- Data register
54-- 100 iaddr r/-/- Last instruction cmon address
55-- *:04 laddr r/-/- line address
56-- 03:00 r/-/- -always zero-
57-- 101 ipc r/-/- Last instruction pc
58-- 110 ireg r/-/- Last instruction
59-- 111 imal r/-/- Last instruction memory access log
60--
61-- data format:
62-- word 8 15 : vm.vmcntl.req
63-- if req = 1
64-- 14 : vm.vmcntl.wacc
65-- 13 : vm.vmcntl.macc
66-- 12 : vm.vmcntl.cacc
67-- 11 : vm.vmcntl.bytop
68-- 10 : vm.vmcntl.dspace
69-- if req = 0
70-- 14 : vm.vmcntl.ack
71-- 13 : vm.vmcntl.err
72-- if ack = 1 and err = 0
73-- 12 : vm.vmcntl.trap_ysv
74-- 11 : vm.vmcntl.trap_mmu
75-- 10 : mwdrop (signals memwait suppress when mwsup=1)
76-- if ack = 0 and err = 1
77-- 12:10 : vm error code (priority encoded, but only one anyone)
78-- 000 err_odd = 1
79-- 001 err_mmu = 1
80-- 010 err_nxm = 1
81-- 011 err_iobto = 1
82-- 100 err_rsv = 1
83--
84-- 09 : se.istart
85-- 08 : se.idone
86--
87-- if imode = 0
88-- 07:00 : se.snum
89-- if imode = 1
90-- 07:00 : cnum
91--
92-- word 7 15:01 : dp.pc (captured at se.istart)
93-- 00 : idecode (is dp.ireg_we delayed by 1 cycle)
94
95-- word 6 15:00 : dp.ireg
96
97-- word 5 15:14 : dp.psw.cmode
98-- 13:12 : dp.psw.pmode
99-- 11 : dp.psw.rset
100-- if imode = 0
101-- 10 : dp.dres valid
102-- 09 : dp.ddst_we
103-- 08 : dp.dsrc_we
104-- if imode = 1
105-- 10 : -- unused --
106-- 09 : -- unused --
107-- 08 : se.vstart
108-- always
109-- 07:05 : dp.psw.pri
110-- 04 : dp.psw.tflag
111-- 03:00 : dp.psw.cc
112
113-- word 4 15:00 : dp.dsrc
114-- word 3 15:00 : dp.ddst
115-- word 2 15:00 : dp.dres (reged)
116-- word 1 15:00 : vm.vmaddr (captured at vm.vmcntl.req)
117-- word 0 15:00 : vm.vmdin or vm.vmdout (captured at req or ack)
118--
119
120library ieee;
121use ieee.std_logic_1164.all;
122use ieee.numeric_std.all;
123
124use work.slvtypes.all;
125use work.memlib.all;
126use work.rblib.all;
127use work.pdp11.all;
128
129-- ----------------------------------------------------------------------------
130
131-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
132-- to control the instantiation. ghdl checks even for not instantiated
133-- entities the validity of generics, that's why natural needed here ....
134
135entity pdp11_dmcmon is -- debug&moni: cpu monitor
136 generic (
137 RB_ADDR : slv16 := rbaddr_dmcmon_off;
138 AWIDTH : natural := 8;
139 SNUM : boolean := false);
140 port (
141 CLK : in slbit; -- clock
142 RESET : in slbit; -- reset
143 RB_MREQ : in rb_mreq_type; -- rbus: request
144 RB_SRES : out rb_sres_type; -- rbus: response
145 DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
146 DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
147 DM_STAT_VM : in dm_stat_vm_type; -- debug and monitor status - vmbox
148 DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
149 );
150end pdp11_dmcmon;
151
152
153architecture syn of pdp11_dmcmon is
154
155 constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
156 constant rbaddr_stat : slv3 := "001"; -- stat address offset
157 constant rbaddr_addr : slv3 := "010"; -- addr address offset
158 constant rbaddr_data : slv3 := "011"; -- data address offset
159 constant rbaddr_iaddr : slv3 := "100"; -- iaddr address offset
160 constant rbaddr_ipc : slv3 := "101"; -- ipc address offset
161 constant rbaddr_ireg : slv3 := "110"; -- ireg address offset
162 constant rbaddr_imal : slv3 := "111"; -- imal address offset
163
164 constant cntl_rbf_mwsup : integer := 5;
165 constant cntl_rbf_imode : integer := 4;
166 constant cntl_rbf_wstop : integer := 3;
167 subtype cntl_rbf_func is integer range 2 downto 0;
168
169 subtype stat_rbf_bsize is integer range 15 downto 13;
170 subtype stat_rbf_malcnt is integer range 12 downto 9;
171 constant stat_rbf_snum : integer := 8;
172 constant stat_rbf_wrap : integer := 2;
173 constant stat_rbf_susp : integer := 1;
174 constant stat_rbf_run : integer := 0;
175
176 subtype addr_rbf_laddr is integer range 4+AWIDTH-1 downto 4;
177 subtype addr_rbf_waddr is integer range 3 downto 0;
178
179 subtype bram_mf_port11 is integer range 143 downto 108;
180 subtype bram_mf_port10 is integer range 107 downto 72;
181 subtype bram_mf_port01 is integer range 71 downto 36;
182 subtype bram_mf_port00 is integer range 35 downto 0;
183
184 subtype bram_df_word8 is integer range 143 downto 128;
185 subtype bram_df_word7 is integer range 127 downto 112;
186 subtype bram_df_word6 is integer range 111 downto 96;
187 subtype bram_df_word5 is integer range 95 downto 80;
188 subtype bram_df_word4 is integer range 79 downto 64;
189 subtype bram_df_word3 is integer range 63 downto 48;
190 subtype bram_df_word2 is integer range 47 downto 32;
191 subtype bram_df_word1 is integer range 31 downto 16;
192 subtype bram_df_word0 is integer range 15 downto 0;
193
194 constant dat8_rbf_req : integer := 15;
195 constant dat8_rbf_wacc : integer := 14; -- if req=1
196 constant dat8_rbf_macc : integer := 13; -- "
197 constant dat8_rbf_cacc : integer := 12; -- "
198 constant dat8_rbf_bytop : integer := 11; -- "
199 constant dat8_rbf_dspace : integer := 10; -- "
200 constant dat8_rbf_ack : integer := 14; -- if req=0
201 constant dat8_rbf_err : integer := 13; -- "
202 constant dat8_rbf_trap_ysv : integer := 12; -- if req=0 ack=1 err=0
203 constant dat8_rbf_trap_mmu : integer := 11; -- "
204 constant dat8_rbf_mwdrop : integer := 10; -- "
205 subtype dat8_rbf_vmerr is integer range 12 downto 10;-- if req=0 ack=0 err=1
206 constant dat8_rbf_istart : integer := 9; -- always
207 constant dat8_rbf_idone : integer := 8; -- "
208
209 constant vmerr_odd : slv3 := "001"; -- vm error code: err_odd
210 constant vmerr_mmu : slv3 := "010"; -- vm error code: err_mmu
211 constant vmerr_nxm : slv3 := "011"; -- vm error code: err_nxm
212 constant vmerr_iobto : slv3 := "100"; -- vm error code: err_iobto
213 constant vmerr_rsv : slv3 := "101"; -- vm error code: err_rsv
214
215 subtype dat8_rbf_snum is integer range 7 downto 0;
216
217 subtype dat8_rbf_cnum is integer range 7 downto 0;
218
219 subtype dat7_rbf_pc is integer range 15 downto 1;
220 constant dat7_rbf_idecode : integer := 0;
221
222 subtype dat5_rbf_cmode is integer range 15 downto 14;
223 subtype dat5_rbf_pmode is integer range 13 downto 12;
224 constant dat5_rbf_rset : integer := 11;
225
226 constant dat5_rbf_dres_val : integer := 10; -- if imode=0
227 constant dat5_rbf_ddst_we : integer := 9;
228 constant dat5_rbf_dsrc_we : integer := 8;
229
230 constant dat5_rbf_vstart : integer := 8; -- if imode=1
231
232 subtype dat5_rbf_pri is integer range 7 downto 5;
233 constant dat5_rbf_tflag : integer := 4;
234 subtype dat5_rbf_cc is integer range 3 downto 0;
235
236 constant func_sto : slv3 := "100"; -- func: stop
237 constant func_sta : slv3 := "101"; -- func: start
238 constant func_sus : slv3 := "110"; -- func: suspend
239 constant func_res : slv3 := "111"; -- func: resume
240
241 constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
242 constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
243
244 type regs_type is record
245 rbsel : slbit; -- rbus select
246 mwsup : slbit; -- mwsup flag (mem wait suppress)
247 imode : slbit; -- imode flag
248 wstop : slbit; -- wstop flag (stop on wrap)
249 susp : slbit; -- suspended flag
250 go : slbit; -- go flag (actively running)
251 active : slbit; -- active flag
252 wrap : slbit; -- laddr wrap flag
253 laddr : slv(AWIDTH-1 downto 0); -- line address
254 waddr : slv4; -- word address
255 cnum : slv8; -- clk counter
256 mal_waddr : slv4; -- mem acc log: write address
257 mal_raddr : slv4; -- mem acc log: read address
258 dp_pc_fet : slv16_1; -- dp.pc_fet (capture on se.istart)
259 dp_pc_dec : slv16_1; -- dp.pc_dec (capture on dp.ireg_we + 1)
260 dp_ireg : slv16; -- dp.ireg
261 dp_ireg_we : slbit; -- dp.ireg_we
262 dp_ireg_we_1 : slbit; -- dp.ireg_we last cycle
263 dp_dres : slv16; -- dp.dres
264 dp_dsrc_we : slbit; -- dp.dsrc_we
265 dp_ddst_we : slbit; -- dp.ddst_we
266 dp_dres_val : slbit; -- dp.dres valid
267 vm_addr : slv16; -- vm.vmaddr
268 vm_din : slv16; -- vm.vmdin
269 vm_dout : slv16; -- vm.vmdout
270 vm_req : slbit; -- vm.vmcntl.req
271 vm_wacc : slbit; -- vm.vmcntl.wacc
272 vm_macc : slbit; -- vm.vmcntl.macc
273 vm_cacc : slbit; -- vm.vmcntl.cacc
274 vm_bytop : slbit; -- vm.vmcntl.bytop
275 vm_dspace : slbit; -- vm.vmcntl.dspace
276 vm_addr_1 : slv16; -- vm.vmaddr last request
277 vm_dout_1 : slv16; -- vm.vmdout last request
278 vm_wacc_1 : slbit; -- vm.vmcntl.wacc last request
279 vm_macc_1 : slbit; -- vm.vmcntl.macc last request
280 vm_cacc_1 : slbit; -- vm.vmcntl.cacc last request
281 vm_bytop_1 : slbit; -- vm.vmcntl.bytop last request
282 vm_dspace_1 : slbit; -- vm.vmcntl.dspace last request
283 vm_ack : slbit; -- vm.vmstat.ack
284 vm_err : slbit; -- vm.vmstat.err
285 vm_err_odd : slbit; -- vm.vmstat.err_odd
286 vm_err_mmu : slbit; -- vm.vmstat.err_mmu
287 vm_err_nxm : slbit; -- vm.vmstat.err_nxm
288 vm_err_iobto : slbit; -- vm.vmstat.err_iobto
289 vm_err_rsv : slbit; -- vm.vmstat.err_rsv
290 vm_trap_ysv : slbit; -- vm.vmstat.trap_ysv
291 vm_trap_mmu : slbit; -- vm.vmstat.trap_mmu
292 vm_pend : slbit; -- vm req pending
293 se_idle : slbit; -- se.idle
294 se_istart : slbit; -- se.istart
295 se_istart_1 : slbit; -- se.istart last cycle
296 se_idone : slbit; -- se.idone
297 se_vstart : slbit; -- se.vstart
298 se_snum : slv8; -- se.snum
299 mwdrop : slbit; -- mem wait drop flag
300 end record regs_type;
301 constant regs_init : regs_type := (
302 '0', -- rbsel
303 '0','1','0', -- mwsup,imode,wstop
304 '0','1','0', -- susp,go,active
305 '0', -- wrap
306 laddrzero, -- laddr
307 "0000", -- waddr
308 (others=>'0'), -- cnum
309 (others=>'0'), -- macwaddr
310 (others=>'0'), -- macraddr
311 (others=>'0'), -- dp_pc_fet
312 (others=>'0'), -- dp_pc_dec
313 (others=>'0'), -- dp_ireq
314 '0','0', -- dp_ireq_we,dp_ireq_we_1
315 (others=>'0'), -- dp_dres
316 '0','0','0', -- dp_dsrc_we,dp_ddst_we,dp_dres_val
317 (others=>'0'), -- vm_addr
318 (others=>'0'), -- vm_din
319 (others=>'0'), -- vm_dout
320 '0','0','0','0','0','0', -- vm_req,..,vm_dspace
321 (others=>'0'), -- vm_addr_1
322 (others=>'0'), -- vm_dout_1
323 '0','0','0','0','0', -- vm_wacc_1,..,vm_dspace_1
324 '0','0', -- vm_ack,vm_err
325 '0','0','0','0','0', -- vm_err_*
326 '0','0', -- vm_trap_*
327 '0', -- vm_pend
328 '0','0','0', -- se_idle,se_istart(_1)
329 '0','0', -- se_idone,se_vstart
330 (others=>'0'), -- se_snum
331 '0' -- mwdrop
332 );
333
334 signal R_REGS : regs_type := regs_init; -- state registers
335 signal N_REGS : regs_type := regs_init; -- next value state regs
336
337 signal BRAM_EN : slbit := '0';
338 signal BRAM_WE : slbit := '0';
339 signal BRAM_ADDRA : slv(AWIDTH downto 0) := (others=>'0');
340 signal BRAM_ADDRB : slv(AWIDTH downto 0) := (others=>'0');
341 signal BRAM_DI : slv(143 downto 0) := (others=>'0');
342 signal BRAM_DO : slv(143 downto 0) := (others=>'0');
343
344 signal MAL_WE : slbit := '0';
345 signal MAL_DI : slv16 := (others=>'0');
346 signal MAL_DO : slv16 := (others=>'0');
347
348 begin
349
350 assert AWIDTH>=8 and AWIDTH<=11
351 report "assert(AWIDTH>=8 and AWIDTH<=11): unsupported AWIDTH"
352 severity failure;
353
355 generic map (
356 AWIDTH => AWIDTH+1,
357 DWIDTH => 36)
358 port map (
359 CLKA => CLK,
360 CLKB => CLK,
361 ENA => BRAM_EN,
362 ENB => BRAM_EN,
363 WEA => BRAM_WE,
364 WEB => BRAM_WE,
365 ADDRA => BRAM_ADDRA,
366 ADDRB => BRAM_ADDRB,
371 );
372
374 generic map (
375 AWIDTH => AWIDTH+1,
376 DWIDTH => 36)
377 port map (
378 CLKA => CLK,
379 CLKB => CLK,
380 ENA => BRAM_EN,
381 ENB => BRAM_EN,
382 WEA => BRAM_WE,
383 WEB => BRAM_WE,
384 ADDRA => BRAM_ADDRA,
385 ADDRB => BRAM_ADDRB,
390 );
391
393 generic map (
394 AWIDTH => 4,
395 DWIDTH => 16)
396 port map (
397 CLK => CLK,
398 WE => MAL_WE,
399 ADDRA => R_REGS.mal_waddr,
400 ADDRB => R_REGS.mal_raddr,
401 DI => MAL_DI,
402 DOA => open,
404
405 proc_regs: process (CLK)
406 begin
407
408 if rising_edge(CLK) then
409 if RESET = '1' then
410 R_REGS <= regs_init;
411 else
412 R_REGS <= N_REGS;
413 end if;
414 end if;
415
416 end process proc_regs;
417
418 proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
419 DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
420 DM_STAT_VM, DM_STAT_VM.vmcntl, DM_STAT_VM.vmstat,
422
423 variable r : regs_type := regs_init;
424 variable n : regs_type := regs_init;
425 variable irb_ack : slbit := '0';
426 variable irb_err : slbit := '0'; -- FIXME: needed ??
427 variable irb_busy : slbit := '0'; -- FIXME: needed ??
428 variable irb_dout : slv16 := (others=>'0');
429 variable irbena : slbit := '0';
430 variable ibramen : slbit := '0'; -- BRAM enable
431 variable ibramwe : slbit := '0'; -- BRAN we
432 variable igoeff : slbit := '0';
433 variable iactive : slbit := '0';
434 variable itake : slbit := '0';
435 variable laddr_inc : slbit := '0';
436 variable idat : slv(143 downto 0) := (others=>'0');
437 variable idat8 : slv16 := (others=>'0');
438 variable idat7 : slv16 := (others=>'0');
439 variable idat5 : slv16 := (others=>'0');
440 variable ivmerr : slv3 := (others=>'0');
441
442 variable imal_we : slbit := '0';
443 variable imal_re : slbit := '0';
444 variable imal_di : slv16 := (others=>'0');
445 variable imal_waddr_clr : slbit := '0';
446 variable imal_raddr_clr : slbit := '0';
447
448 begin
449
450 r := R_REGS;
451 n := R_REGS;
452
453 irb_ack := '0';
454 irb_err := '0';
455 irb_busy := '0';
456 irb_dout := (others=>'0');
457 irbena := RB_MREQ.re or RB_MREQ.we;
458
459 ibramen := '0';
460 ibramwe := '0';
461
462 igoeff := '0';
463 iactive := '0';
464 itake := '0';
465
466 laddr_inc := '0';
467
468 imal_we := '0';
469 imal_re := '0';
470 imal_di := r.vm_addr;
471 imal_waddr_clr := '0';
472 imal_raddr_clr := '0';
473
474 -- rbus address decoder
475 n.rbsel := '0';
476 if RB_MREQ.aval='1' and RB_MREQ.addr(12 downto 3)=RB_ADDR(12 downto 3) then
477 n.rbsel := '1';
478 ibramen := '1'; -- ensure bram read before rbus read
479 end if;
480
481 -- rbus transactions
482 if r.rbsel = '1' then
483 irb_ack := irbena; -- ack all accesses
484 case RB_MREQ.addr(2 downto 0) is
485 when rbaddr_cntl => -- cntl ------------------
486 if RB_MREQ.we = '1' then
487 case RB_MREQ.din(cntl_rbf_func) is
488 when func_sto => -- func: stop ------------
489 n.go := '0';
490 n.susp := '0';
491 when func_sta => -- func: start -----------
492 n.mwsup := RB_MREQ.din(cntl_rbf_mwsup);
493 n.imode := RB_MREQ.din(cntl_rbf_imode);
494 n.wstop := RB_MREQ.din(cntl_rbf_wstop);
495 n.go := '1';
496 n.susp := '0';
497 n.wrap := '0';
498 n.laddr := laddrzero;
499 n.waddr := "0000";
500 when func_sus => -- func: susp ------------
501 if r.go = '1' then -- noop unless running
502 n.go := '0';
503 n.susp := r.go;
504 end if;
505 when func_res => -- func: resu ------------
506 n.go := r.susp;
507 n.susp := '0';
508 when others => null; -- <> --------------------
509 end case;
510 end if;
511
512 when rbaddr_stat => -- stat ------------------
513 irb_err := RB_MREQ.we;
514
515 when rbaddr_addr => -- addr ------------------
516 if RB_MREQ.we = '1' then
517 if r.go = '0' then -- if not active OK
518 n.laddr := RB_MREQ.din(addr_rbf_laddr);
519 n.waddr := RB_MREQ.din(addr_rbf_waddr);
520 else
521 irb_err := '1'; -- otherwise error
522 end if;
523 end if;
524
525 when rbaddr_data => -- data ------------------
526 -- write to data is an error
527 if RB_MREQ.we='1' then
528 irb_err := '1'; -- error
529 end if;
530 -- read to data always allowed, addr only incremented when not active
531 if RB_MREQ.re = '1' and r.go = '0' then
532 if r.waddr(3) = '1' then -- equivalent waddr>=1000
533 n.waddr := (others=>'0');
534 laddr_inc := '1';
535 else
536 n.waddr := slv(unsigned(r.waddr) + 1);
537 end if;
538 end if;
539
540 when rbaddr_iaddr => -- iaddr -----------------
541 irb_err := RB_MREQ.we;
542
543 when rbaddr_ipc => -- ipc -------------------
544 irb_err := RB_MREQ.we;
545
546 when rbaddr_ireg => -- ireg ------------------
547 irb_err := RB_MREQ.we;
548
549 when rbaddr_imal => -- imal ------------------
550 irb_err := RB_MREQ.we;
551 imal_re := RB_MREQ.re;
552
553 when others => null; -- <> --------------------
554 end case;
555 end if;
556
557 -- rbus output driver
558 if r.rbsel = '1' then
559 case RB_MREQ.addr(2 downto 0) is
560
561 when rbaddr_cntl => -- cntl ------------------
562 irb_dout(cntl_rbf_mwsup) := r.mwsup;
563 irb_dout(cntl_rbf_imode) := r.imode;
564 irb_dout(cntl_rbf_wstop) := r.wstop;
565
566 when rbaddr_stat => -- stat ------------------
567 irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-8,3));
568 irb_dout(stat_rbf_malcnt) := r.mal_waddr;
569 if SNUM then
570 irb_dout(stat_rbf_snum) := '1';
571 end if;
572 irb_dout(stat_rbf_wrap) := r.wrap;
573 irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
574 irb_dout(stat_rbf_run) := r.go or r.susp; -- started
575
576 when rbaddr_addr => -- addr ------------------
577 irb_dout(addr_rbf_laddr) := r.laddr;
578 irb_dout(addr_rbf_waddr) := r.waddr;
579
580 when rbaddr_data => -- data ------------------
581 case r.waddr is
582 when "1000" => irb_dout := BRAM_DO(bram_df_word8);
583 when "0111" => irb_dout := BRAM_DO(bram_df_word7);
584 when "0110" => irb_dout := BRAM_DO(bram_df_word6);
585 when "0101" => irb_dout := BRAM_DO(bram_df_word5);
586 when "0100" => irb_dout := BRAM_DO(bram_df_word4);
587 when "0011" => irb_dout := BRAM_DO(bram_df_word3);
588 when "0010" => irb_dout := BRAM_DO(bram_df_word2);
589 when "0001" => irb_dout := BRAM_DO(bram_df_word1);
590 when "0000" => irb_dout := BRAM_DO(bram_df_word0);
591 when others => irb_dout := (others=>'0');
592 end case;
593
594 when rbaddr_iaddr => -- iaddr -----------------
595 null; -- FIXME_code: implement
596
597 when rbaddr_ipc => -- ipc -------------------
598 irb_dout(r.dp_pc_dec'range) := r.dp_pc_dec;
599 n.mal_raddr := (others=>'0');
600
601 when rbaddr_ireg => -- ireg ------------------
602 irb_dout := r.dp_ireg;
603
604 when rbaddr_imal => -- imal ------------------
605 irb_dout := MAL_DO;
606
607 when others => null;
608 end case;
609 end if;
610
611 -- cpu monitor
612
613 -- capture CPU state signals which are combinatorial logic
614 if DM_STAT_SE.istart = '1' then
615 n.dp_pc_fet := DM_STAT_DP.pc(15 downto 1);
616 end if;
617 n.dp_ireg := DM_STAT_DP.ireg;
618 n.dp_ireg_we := DM_STAT_DP.ireg_we;
619 n.dp_ireg_we_1 := r.dp_ireg_we;
620 if r.dp_ireg_we = '1' then -- dp_pc_dec update when dp_ireg changes
621 n.dp_pc_dec := r.dp_pc_fet;
622 end if;
623
624 n.dp_dsrc_we := DM_STAT_DP.dsrc_we;
625 n.dp_ddst_we := DM_STAT_DP.ddst_we;
626 n.dp_dres_val := '0';
627 if ((DM_STAT_DP.gr_we or DM_STAT_DP.psr_we or -- capture dres only when
628 DM_STAT_DP.dsrc_we or DM_STAT_DP.ddst_we or -- actually used
629 DM_STAT_DP.dtmp_we or DM_STAT_DP.cpdout_we or
630 DM_STAT_VM.vmcntl.req) = '1') then
631 n.dp_dres := DM_STAT_DP.dres;
632 n.dp_dres_val := '1';
633 end if;
634
635 n.vm_req := DM_STAT_VM.vmcntl.req;
636 -- capture vm request data when vm_req asserted, need them in later cycles
637 -- don't update vmaddr for write part of rmw sequence
638 -- no valid address vmaddr given, address is kept in vmbox
639 if DM_STAT_VM.vmcntl.req = '1' then
640 n.vm_wacc_1 := r.vm_wacc;
641 n.vm_macc_1 := r.vm_macc;
642 n.vm_cacc_1 := r.vm_cacc;
643 n.vm_bytop_1 := r.vm_bytop;
644 n.vm_dspace_1 := r.vm_dspace;
645 n.vm_wacc := DM_STAT_VM.vmcntl.wacc;
646 n.vm_macc := DM_STAT_VM.vmcntl.macc;
647 n.vm_cacc := DM_STAT_VM.vmcntl.cacc;
648 n.vm_bytop := DM_STAT_VM.vmcntl.bytop;
649 n.vm_dspace := DM_STAT_VM.vmcntl.dspace;
650 if (DM_STAT_VM.vmcntl.macc and DM_STAT_VM.vmcntl.wacc) = '0' then
651 n.vm_addr_1 := r.vm_addr;
652 n.vm_addr := DM_STAT_VM.vmaddr;
653 end if;
654 n.vm_din := DM_STAT_VM.vmdin;
655 end if;
656 n.vm_ack := DM_STAT_VM.vmstat.ack;
657 n.vm_err := DM_STAT_VM.vmstat.err;
658 if DM_STAT_VM.vmstat.ack = '1' then
659 n.vm_dout_1 := r.vm_dout;
660 n.vm_dout := DM_STAT_VM.vmdout;
661 n.vm_trap_ysv := DM_STAT_VM.vmstat.trap_ysv;
662 n.vm_trap_mmu := DM_STAT_VM.vmstat.trap_mmu;
663 end if;
664 if DM_STAT_VM.vmstat.err = '1' then
665 n.vm_err_odd := DM_STAT_VM.vmstat.err_odd;
666 n.vm_err_mmu := DM_STAT_VM.vmstat.err_mmu;
667 n.vm_err_nxm := DM_STAT_VM.vmstat.err_nxm;
668 n.vm_err_iobto := DM_STAT_VM.vmstat.err_iobto;
669 n.vm_err_rsv := DM_STAT_VM.vmstat.err_rsv;
670 end if;
671
672 n.se_istart_1 := r.se_istart;
673 n.se_idle := DM_STAT_SE.idle;
674 n.se_istart := DM_STAT_SE.istart;
675 n.se_idone := DM_STAT_SE.idone;
676 n.se_vstart := DM_STAT_SE.vstart;
677 n.se_snum := DM_STAT_SE.snum;
678
679 -- active state logic
680 igoeff := '0';
681 if r.go = '1' then
682 if DM_STAT_CO.cpugo='1' and DM_STAT_CO.cpususp='0' then
683 igoeff := '1';
684 end if;
685 if DM_STAT_CO.cpustep = '1' then
686 igoeff := '1';
687 end if;
688 end if;
689
690 iactive := r.active;
691 if r.se_idle = '1' then -- in idle state
692 if igoeff = '0' then -- if goeff=0 stop running
693 n.active := '0';
694 end if;
695 else -- in non-idle state
696 if igoeff = '1' then -- if goerr=1 start running
697 iactive := '1';
698 n.active := '1';
699 end if;
700 end if;
701
702 if r.vm_req = '1' then
703 n.mwdrop := '0';
704 n.vm_pend := '1';
705 elsif (r.vm_ack or r.vm_err) = '1' then
706 n.vm_pend := '0';
707 end if;
708
709 itake := '0';
710 if r.imode = '0' then -- imode=0
711 itake := '1'; -- take all
712 if r.mwsup = '1' then -- if mem wait suppress
713 if (r.vm_pend and not (r.vm_ack or r.vm_err)) = '1' then
714 itake := '0';
715 n.mwdrop := '1';
716 end if;
717 end if;
718 else -- imode=1
719 itake := r.se_idone or r.se_vstart or r.vm_err;
720 end if;
721
722 if iactive='1' and itake='1' then -- active and enabled
723 ibramen := '1';
724 ibramwe := '1';
725 laddr_inc := '1';
726 end if;
727
728 if laddr_inc = '1' then
729 n.laddr := slv(unsigned(r.laddr) + 1);
730 if r.go='1' and r.laddr=laddrlast then
731 n.wrap := '1';
732 if r.wstop = '1' then
733 n.go := '0';
734 end if;
735 end if;
736 end if;
737
738 -- last but not least: the clock cycle counter
739 n.cnum := slv(unsigned(r.cnum) + 1);
740
741 -- now build memory data word
742 idat := (others=>'0');
743
744 -- encode vm errors
745 ivmerr := (others=>'0');
746 if r.vm_err_odd = '1' then
747 ivmerr := vmerr_odd;
748 elsif r.vm_err_mmu = '1' then
749 ivmerr := vmerr_mmu;
750 elsif r.vm_err_nxm = '1' then
751 ivmerr := vmerr_nxm;
752 elsif r.vm_err_iobto = '1' then
753 ivmerr := vmerr_iobto;
754 elsif r.vm_err_rsv = '1' then
755 ivmerr := vmerr_rsv;
756 end if;
757
758 -- Note for imode=1
759 -- Write vm request data unless there is an error.
760 -- If in current or last cycle a ifetch (istart=1) was done use
761 -- attributes of previous request. If last cycle was an ifetch
762 -- and vm_ack set use also previous data. That ensures that the
763 -- values of current instruction are shown, and not of pre-fetch
764
765 -- build word8
766 idat8 := (others=>'0');
767 if r.vm_req = '1' or (r.imode='1' and r.vm_err='0') then
768 idat8(dat8_rbf_req) := '1';
769 if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
770 idat8(dat8_rbf_wacc) := R_REGS.vm_wacc_1;
771 idat8(dat8_rbf_macc) := R_REGS.vm_macc_1;
772 idat8(dat8_rbf_cacc) := R_REGS.vm_cacc_1;
773 idat8(dat8_rbf_bytop) := R_REGS.vm_bytop_1;
774 idat8(dat8_rbf_dspace) := R_REGS.vm_dspace_1;
775 else
776 idat8(dat8_rbf_wacc) := R_REGS.vm_wacc;
777 idat8(dat8_rbf_macc) := R_REGS.vm_macc;
778 idat8(dat8_rbf_cacc) := R_REGS.vm_cacc;
779 idat8(dat8_rbf_bytop) := R_REGS.vm_bytop;
780 idat8(dat8_rbf_dspace) := R_REGS.vm_dspace;
781 end if;
782 else
783 idat8(dat8_rbf_ack) := R_REGS.vm_ack;
784 idat8(dat8_rbf_err) := R_REGS.vm_err;
785 if r.vm_ack = '1' then
786 idat8(dat8_rbf_trap_ysv) := R_REGS.vm_trap_ysv;
787 idat8(dat8_rbf_trap_mmu) := R_REGS.vm_trap_mmu;
788 idat8(dat8_rbf_mwdrop) := R_REGS.mwdrop;
789 elsif r.vm_err = '1' then
790 idat8(dat8_rbf_vmerr) := ivmerr;
791 end if;
792 end if;
793 idat8(dat8_rbf_istart) := R_REGS.se_istart;
794 idat8(dat8_rbf_idone) := R_REGS.se_idone;
795
796 if r.imode = '0' then
797 idat8(dat8_rbf_snum) := R_REGS.se_snum;
798 else
799 idat8(dat8_rbf_cnum) := R_REGS.cnum;
800 end if;
801 idat(bram_df_word8) := idat8;
802
803 -- build word7
804 idat7 := (others=>'0');
805 idat7(dat7_rbf_pc) := R_REGS.dp_pc_dec;
806 idat7(dat7_rbf_idecode):= R_REGS.dp_ireg_we_1;
807 idat(bram_df_word7) := idat7;
808
809 -- build word6
810 idat(bram_df_word6) := R_REGS.dp_ireg;
811
812 -- build word5
813 idat5 := (others=>'0');
814 idat5(dat5_rbf_cmode) := DM_STAT_DP.psw.cmode;
815 idat5(dat5_rbf_pmode) := DM_STAT_DP.psw.pmode;
816 idat5(dat5_rbf_rset) := DM_STAT_DP.psw.rset;
817 if r.imode = '0' then
818 idat5(dat5_rbf_dres_val) := R_REGS.dp_dres_val;
819 idat5(dat5_rbf_ddst_we) := R_REGS.dp_ddst_we;
820 idat5(dat5_rbf_dsrc_we) := R_REGS.dp_dsrc_we;
821 else
822 idat5(dat5_rbf_vstart) := R_REGS.se_vstart;
823 end if;
824 idat5(dat5_rbf_pri) := DM_STAT_DP.psw.pri;
825 idat5(dat5_rbf_tflag) := DM_STAT_DP.psw.tflag;
826 idat5(dat5_rbf_cc) := DM_STAT_DP.psw.cc;
827 idat(bram_df_word5) := idat5;
828
829 -- build word4 to word2
830 idat(bram_df_word4) := DM_STAT_DP.dsrc;
831 idat(bram_df_word3) := DM_STAT_DP.ddst;
832 idat(bram_df_word2) := R_REGS.dp_dres;
833
834 -- build word1
835 if r.imode = '1' and (r.se_istart='1' or r.se_istart_1='1') then
836 idat(bram_df_word1) := R_REGS.vm_addr_1;
837 else
838 idat(bram_df_word1) := R_REGS.vm_addr;
839 end if;
840
841 -- build word0
842 if r.vm_wacc = '1' then
843 idat(bram_df_word0) := R_REGS.vm_din;
844 else
845 if r.imode = '1' and r.se_istart_1 = '1' and r.vm_ack = '1' then
846 idat(bram_df_word0) := R_REGS.vm_dout_1;
847 else
848 idat(bram_df_word0) := R_REGS.vm_dout;
849 end if;
850 end if;
851
852 -- finally memory access log buffer logic
853 if r.vm_cacc = '0' then
854 if r.vm_req = '1' then
855 imal_we := '1';
856 imal_di := r.vm_addr;
857 elsif r.vm_ack='1' then
858 imal_we := '1';
859 if r.vm_wacc='1' then
860 imal_di := r.vm_din;
861 else
862 imal_di := r.vm_dout;
863 end if;
864 if r.vm_bytop = '1' then -- for byte read/write data
865 imal_di(15 downto 8) := (others=>'0'); -- zero msb (is undefined)
866 end if;
867 end if;
868 end if;
869
870 imal_waddr_clr := r.dp_ireg_we; -- FIXME: very preliminary !!!
871
872 if imal_waddr_clr = '1' then
873 n.mal_waddr := (others=>'0');
874 elsif imal_we = '1' then
875 n.mal_waddr := slv(unsigned(r.mal_waddr) + 1);
876 end if;
877
878 if imal_raddr_clr = '1' then
879 n.mal_raddr := (others=>'0');
880 elsif imal_re = '1' then
881 n.mal_raddr := slv(unsigned(r.mal_raddr) + 1);
882 end if;
883
884 N_REGS <= n;
885
886 BRAM_EN <= ibramen;
887 BRAM_WE <= ibramwe;
888 BRAM_ADDRA <= '0' & R_REGS.laddr;
889 BRAM_ADDRB <= '1' & R_REGS.laddr;
890 BRAM_DI <= idat;
891
892 MAL_WE <= imal_we;
893 MAL_DI <= imal_di;
894
895 RB_SRES.ack <= irb_ack;
896 RB_SRES.err <= irb_err;
897 RB_SRES.busy <= irb_busy;
898 RB_SRES.dout <= irb_dout;
899
900 end process proc_next;
901
902end syn;
integer := 8 dat5_rbf_dsrc_we
integer := 8 dat5_rbf_vstart
slv3 := "100" rbaddr_iaddr
integer range 15 downto 14 dat5_rbf_cmode
slbit := '0' MAL_WE
integer range 127 downto 112 bram_df_word7
integer := 14 dat8_rbf_wacc
integer := 15 dat8_rbf_req
slv3 := "100" func_sto
integer range 7 downto 5 dat5_rbf_pri
slv3 := "101" rbaddr_ipc
regs_type :=( '0', '0', '1', '0', '0', '1', '0', '0', laddrzero, "0000",( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'),( others => '0'), '0', '0',( others => '0'), '0', '0', '0',( others => '0'),( others => '0'),( others => '0'), '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'), '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'), '0') regs_init
slbit := '0' BRAM_EN
integer range 111 downto 96 bram_df_word6
integer range 12 downto 10 dat8_rbf_vmerr
integer range 7 downto 0 dat8_rbf_cnum
integer := 14 dat8_rbf_ack
integer range 47 downto 32 bram_df_word2
integer := 2 stat_rbf_wrap
integer := 8 dat8_rbf_idone
integer range 95 downto 80 bram_df_word5
integer := 11 dat5_rbf_rset
integer range 13 downto 12 dat5_rbf_pmode
slv16 :=( others => '0') MAL_DO
integer := 10 dat5_rbf_dres_val
integer range 143 downto 108 bram_mf_port11
integer := 0 dat7_rbf_idecode
integer := 12 dat8_rbf_cacc
integer := 9 dat8_rbf_istart
regs_type := regs_init N_REGS
integer range 12 downto 9 stat_rbf_malcnt
integer := 8 stat_rbf_snum
slv3 := "101" func_sta
slv3 := "111" rbaddr_imal
integer := 4 dat5_rbf_tflag
integer range 143 downto 128 bram_df_word8
integer range 31 downto 16 bram_df_word1
slbit := '0' BRAM_WE
integer := 10 dat8_rbf_dspace
integer := 11 dat8_rbf_trap_mmu
slv3 := "000" rbaddr_cntl
integer := 13 dat8_rbf_err
slv3 := "001" rbaddr_stat
integer range 2 downto 0 cntl_rbf_func
slv( AWIDTH- 1 downto 0) :=( others => '1') laddrlast
slv3 := "010" rbaddr_addr
integer := 4 cntl_rbf_imode
slv( 143 downto 0) :=( others => '0') BRAM_DI
slv3 := "011" rbaddr_data
slv3 := "100" vmerr_iobto
integer := 13 dat8_rbf_macc
regs_type := regs_init R_REGS
integer range 71 downto 36 bram_mf_port01
integer := 11 dat8_rbf_bytop
integer := 3 cntl_rbf_wstop
slv( AWIDTH downto 0) :=( others => '0') BRAM_ADDRA
slv( AWIDTH downto 0) :=( others => '0') BRAM_ADDRB
integer := 12 dat8_rbf_trap_ysv
slv3 := "001" vmerr_odd
integer range 3 downto 0 addr_rbf_waddr
integer range 3 downto 0 dat5_rbf_cc
integer := 1 stat_rbf_susp
integer range 15 downto 0 bram_df_word0
slv3 := "011" vmerr_nxm
integer := 10 dat8_rbf_mwdrop
integer := 5 cntl_rbf_mwsup
integer range 7 downto 0 dat8_rbf_snum
integer range 35 downto 0 bram_mf_port00
slv3 := "111" func_res
slv3 := "110" rbaddr_ireg
integer range 15 downto 13 stat_rbf_bsize
integer range 107 downto 72 bram_mf_port10
slv3 := "110" func_sus
integer range 4+ AWIDTH- 1 downto 4 addr_rbf_laddr
integer range 63 downto 48 bram_df_word3
integer range 79 downto 64 bram_df_word4
slv3 := "010" vmerr_mmu
slv( AWIDTH- 1 downto 0) :=( others => '0') laddrzero
slv16 :=( others => '0') MAL_DI
slv( 143 downto 0) :=( others => '0') BRAM_DO
integer := 9 dat5_rbf_ddst_we
slv3 := "101" vmerr_rsv
integer := 0 stat_rbf_run
integer range 15 downto 1 dat7_rbf_pc
in RESET slbit
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
RB_ADDR slv16 := rbaddr_dmcmon_off
AWIDTH natural := 8
in DM_STAT_SE dm_stat_se_type
in CLK slbit
in RB_MREQ rb_mreq_type
in DM_STAT_VM dm_stat_vm_type
SNUM boolean := false
out RB_SRES rb_sres_type
Definition: pdp11.vhd:123
AWIDTH positive := 4
in DI slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
DWIDTH positive := 16
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 1) slv16_1
Definition: slvtypes.vhd:67
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31