w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_irq.vhd
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1-- $Id: pdp11_irq.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_irq - syn
7-- Description: pdp11: interrupt requester
8--
9-- Dependencies: ib_sel
10-- Test bench: tb/tb_pdp11_core (implicit)
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2019-04-23 1136 1.3 BUGFIX: re-write, ensure ACK send to correct device
17-- 2011-11-18 427 1.2.2 now numeric_std clean
18-- 2010-10-23 335 1.2.1 use ib_sel
19-- 2010-10-17 333 1.2 use ibus V2 interface
20-- 2008-08-22 161 1.1.4 use iblib
21-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
22-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
23-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
24-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
25-- 2007-10-12 88 1.0.2 avoid ieee.std_logic_unsigned, use cast to unsigned
26-- 2007-06-14 56 1.0.1 Use slvtypes.all
27-- 2007-05-12 26 1.0 Initial version
28------------------------------------------------------------------------------
29
30library ieee;
31use ieee.std_logic_1164.all;
32use ieee.numeric_std.all;
33
34use work.slvtypes.all;
35use work.iblib.all;
36use work.pdp11.all;
37
38-- ----------------------------------------------------------------------------
39
40entity pdp11_irq is -- interrupt requester
41 port (
42 CLK : in slbit; -- clock
43 BRESET : in slbit; -- bus reset
44 INT_ACK : in slbit; -- interrupt acknowledge from CPU
45 EI_PRI : in slv3; -- external interrupt priority
46 EI_VECT : in slv9_2; -- external interrupt vector
47 EI_ACKM : out slbit; -- external interrupt acknowledge
48 PRI : out slv3; -- interrupt priority
49 VECT : out slv9_2; -- interrupt vector
50 IB_MREQ : in ib_mreq_type; -- ibus request
51 IB_SRES : out ib_sres_type -- ibus response
52 );
53end pdp11_irq;
54
55architecture syn of pdp11_irq is
56
57 constant ibaddr_pirq : slv16 := slv(to_unsigned(8#177772#,16));
58 constant vect_pirq : slv9 := slv(to_unsigned(8#240#,9));
59
60 subtype pirq_ibf_pir is integer range 15 downto 9;
61 subtype pirq_ibf_pia_h is integer range 7 downto 5;
62 subtype pirq_ibf_pia_l is integer range 3 downto 1;
63
64 type regs_type is record -- state registers
65 pirq : slv8_1; -- pirq mask
66 eilast : slbit; -- ei won in last cycle
67 end record regs_type;
68
69 constant regs_init : regs_type := (
70 (others=>'0'), -- pirq
71 '0' -- eilast
72 );
73
76
77 signal IBSEL_PIRQ : slbit := '0';
78 signal PI_PRI : slv3 := (others => '0'); -- prog.int. priority
79
80-- attribute PRIORITY_EXTRACT : string;
81-- attribute PRIORITY_EXTRACT of PI_PRI : signal is "force";
82
83begin
84
85 SEL : ib_sel
86 generic map (
88 port map (
89 CLK => CLK,
92 );
93
94 proc_regs: process (CLK)
95 begin
96 if rising_edge(CLK) then
97 if BRESET = '1' then
99 else
100 R_REGS <= N_REGS;
101 end if;
102 end if;
103 end process proc_regs;
104
105 PI_PRI <= "111" when R_REGS.pirq(7)='1' else
106 "110" when R_REGS.pirq(6)='1' else
107 "101" when R_REGS.pirq(5)='1' else
108 "100" when R_REGS.pirq(4)='1' else
109 "011" when R_REGS.pirq(3)='1' else
110 "010" when R_REGS.pirq(2)='1' else
111 "001" when R_REGS.pirq(1)='1' else
112 "000";
113
114 proc_next : process (R_REGS, IB_MREQ, IBSEL_PIRQ, PI_PRI,
116 variable r : regs_type := regs_init;
117 variable n : regs_type := regs_init;
118 variable idout : slv16 := (others=>'0');
119 variable ibreq : slbit := '0';
120 begin
121
122 r := R_REGS;
123 n := R_REGS;
124
125 idout := (others=>'0');
126 ibreq := IB_MREQ.re or IB_MREQ.we;
127
128 -- ibus transactions
129 if IBSEL_PIRQ = '1' then
130
131 idout(pirq_ibf_pir) := r.pirq;
132 idout(pirq_ibf_pia_h) := PI_PRI;
133 idout(pirq_ibf_pia_l) := PI_PRI;
134
135 if IB_MREQ.we='1'and IB_MREQ.be1='1' then
136 n.pirq := IB_MREQ.din(pirq_ibf_pir);
137 end if;
138 end if;
139
140 -- pirq vs ei_vect selection
141 if unsigned(EI_PRI) > unsigned(PI_PRI) then
142 n.eilast := '1';
143 PRI <= EI_PRI;
144 VECT <= EI_VECT;
145 else
146 n.eilast := '0';
147 PRI <= PI_PRI;
148 VECT <= vect_pirq(8 downto 2);
149 end if;
150
151 -- Note: INT_ACK comes one cycle after vector is latched !
152 -- therefore send INT_ACK to EI_ACKM only if EI was winner in last cycle
153 EI_ACKM <= '0';
154 if r.eilast = '1' then
155 EI_ACKM <= INT_ACK;
156 end if;
157
158 N_REGS <= n;
159
160 IB_SRES.dout <= idout;
161 IB_SRES.ack <= IBSEL_PIRQ and ibreq; -- ack all
162 IB_SRES.busy <= '0';
163
164 end process proc_next;
165
166end syn;
out SEL slbit
Definition: ib_sel.vhd:35
IB_ADDR slv16
Definition: ib_sel.vhd:29
in CLK slbit
Definition: ib_sel.vhd:32
in IB_MREQ ib_mreq_type
Definition: ib_sel.vhd:33
Definition: iblib.vhd:33
regs_type := regs_init N_REGS
Definition: pdp11_irq.vhd:75
slv16 := slv( to_unsigned( 8#177772#, 16) ) ibaddr_pirq
Definition: pdp11_irq.vhd:57
integer range 3 downto 1 pirq_ibf_pia_l
Definition: pdp11_irq.vhd:62
slbit := '0' IBSEL_PIRQ
Definition: pdp11_irq.vhd:77
slv3 :=( others => '0') PI_PRI
Definition: pdp11_irq.vhd:78
integer range 15 downto 9 pirq_ibf_pir
Definition: pdp11_irq.vhd:60
regs_type := regs_init R_REGS
Definition: pdp11_irq.vhd:74
integer range 7 downto 5 pirq_ibf_pia_h
Definition: pdp11_irq.vhd:61
slv9 := slv( to_unsigned( 8#240#, 9) ) vect_pirq
Definition: pdp11_irq.vhd:58
regs_type :=(( others => '0'), '0') regs_init
Definition: pdp11_irq.vhd:69
in BRESET slbit
Definition: pdp11_irq.vhd:43
out EI_ACKM slbit
Definition: pdp11_irq.vhd:47
out PRI slv3
Definition: pdp11_irq.vhd:48
in INT_ACK slbit
Definition: pdp11_irq.vhd:44
in CLK slbit
Definition: pdp11_irq.vhd:42
in IB_MREQ ib_mreq_type
Definition: pdp11_irq.vhd:50
out IB_SRES ib_sres_type
Definition: pdp11_irq.vhd:52
in EI_VECT slv9_2
Definition: pdp11_irq.vhd:46
in EI_PRI slv3
Definition: pdp11_irq.vhd:45
out VECT slv9_2
Definition: pdp11_irq.vhd:49
Definition: pdp11.vhd:123
std_logic_vector( 7 downto 1) slv8_1
Definition: slvtypes.vhd:64
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 8 downto 2) slv9_2
Definition: slvtypes.vhd:65
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31