31use ieee.std_logic_1164.
all;
32use ieee.numeric_std.
all;
94 proc_regs:
process (
CLK)
96 if rising_edge(CLK) then
103 end process proc_regs;
106 "110" when R_REGS.pirq(6)='1' else
107 "101" when R_REGS.pirq(5)='1' else
108 "100" when R_REGS.pirq(4)='1' else
109 "011" when R_REGS.pirq(3)='1' else
110 "010" when R_REGS.pirq(2)='1' else
111 "001" when R_REGS.pirq(1)='1' else
118 variable idout : slv16 := (others=>'0');
119 variable ibreq : slbit := '0';
125 idout := (others=>'0');
154 if r.eilast = '1' then
164 end process proc_next;
regs_type := regs_init N_REGS
slv16 := slv( to_unsigned( 8#177772#, 16) ) ibaddr_pirq
integer range 3 downto 1 pirq_ibf_pia_l
slv3 :=( others => '0') PI_PRI
integer range 15 downto 9 pirq_ibf_pir
regs_type := regs_init R_REGS
integer range 7 downto 5 pirq_ibf_pia_h
slv9 := slv( to_unsigned( 8#240#, 9) ) vect_pirq
regs_type :=(( others => '0'), '0') regs_init
std_logic_vector( 7 downto 1) slv8_1
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 8 downto 2) slv9_2
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 15 downto 0) slv16