24use ieee.std_logic_1164.
all;
25use ieee.numeric_std.
all;
86 proc_regs:
process (
CLK)
88 if rising_edge(CLK) then
95 end process proc_regs;
100 variable idout : slv16 := (others=>'0');
101 variable ibreq : slbit := '0';
102 variable ibw0 : slbit := '0';
108 idout := (others=>'0');
137 if r.ibsel_cr = '1' then
143 if r.ibsel_hm = '1' then
144 idout(r.hm_data'range) := r.hm_data;
146 if r.ibsel_ls = '1' then
147 idout := slv(to_unsigned(sys_conf_mem_losize,16));
150 if r.ibsel_cr='1' and ibw0='1' then
158 n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
164 IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
165 r.ibsel_ls or r.ibsel_nn) and ibreq;
168 end process proc_next;
slv16 := slv( to_unsigned( 8#177762#, 16) ) ibaddr_hisize
integer range 5 downto 4 cntl_ibf_frep
regs_type :=( '0', '0', '0', '0',( others => '0'), "00", "00", '0', '0') regs_init
slv16 := slv( to_unsigned( 8#177744#, 16) ) ibaddr_syserr
slv16 := slv( to_unsigned( 8#177740#, 16) ) ibaddr_loaddr
regs_type := regs_init N_REGS
integer := 1 cntl_ibf_disutrap
integer range 3 downto 2 cntl_ibf_fmiss
slv16 := slv( to_unsigned( 8#177750#, 16) ) ibaddr_maint
regs_type := regs_init R_REGS
slv16 := slv( to_unsigned( 8#177752#, 16) ) ibaddr_hm
integer := 0 cntl_ibf_distrap
slv16 := slv( to_unsigned( 8#177760#, 16) ) ibaddr_losize
slv16 := slv( to_unsigned( 8#177746#, 16) ) ibaddr_cntl
slv16 := slv( to_unsigned( 8#177742#, 16) ) ibaddr_hiaddr
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 5 downto 0) slv6
std_logic_vector( 1 downto 0) slv2