w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_mem70.vhd
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1-- $Id: pdp11_mem70.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_mem70 - syn
7-- Description: pdp11: 11/70 memory system registers
8--
9-- Dependencies: -
10-- Test bench: tb/tb_pdp11_core (implicit)
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2011-11-18 427 1.1.1 now numeric_std clean
17-- 2010-10-17 333 1.1 use ibus V2 interface
18-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
19-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
20-- 2008-01-27 115 1.0 Initial version
21------------------------------------------------------------------------------
22
23library ieee;
24use ieee.std_logic_1164.all;
25use ieee.numeric_std.all;
26
27use work.slvtypes.all;
28use work.iblib.all;
29use work.pdp11.all;
30use work.sys_conf.all;
31
32-- ----------------------------------------------------------------------------
33
34entity pdp11_mem70 is -- 11/70 memory system registers
35 port (
36 CLK : in slbit; -- clock
37 CRESET : in slbit; -- cpu reset
38 HM_ENA : in slbit; -- hit/miss enable
39 HM_VAL : in slbit; -- hit/miss value
40 CACHE_FMISS : out slbit; -- cache force miss
41 IB_MREQ : in ib_mreq_type; -- ibus request
42 IB_SRES : out ib_sres_type -- ibus response
43 );
44end pdp11_mem70;
45
46architecture syn of pdp11_mem70 is
47
48 constant ibaddr_loaddr : slv16 := slv(to_unsigned(8#177740#,16));
49 constant ibaddr_hiaddr : slv16 := slv(to_unsigned(8#177742#,16));
50 constant ibaddr_syserr : slv16 := slv(to_unsigned(8#177744#,16));
51 constant ibaddr_cntl : slv16 := slv(to_unsigned(8#177746#,16));
52 constant ibaddr_maint : slv16 := slv(to_unsigned(8#177750#,16));
53 constant ibaddr_hm : slv16 := slv(to_unsigned(8#177752#,16));
54 constant ibaddr_losize : slv16 := slv(to_unsigned(8#177760#,16));
55 constant ibaddr_hisize : slv16 := slv(to_unsigned(8#177762#,16));
56
57 subtype cntl_ibf_frep is integer range 5 downto 4;
58 subtype cntl_ibf_fmiss is integer range 3 downto 2;
59 constant cntl_ibf_disutrap : integer := 1;
60 constant cntl_ibf_distrap : integer := 0;
61
62 type regs_type is record -- state registers
63 ibsel_cr : slbit; -- ibus select cntl
64 ibsel_hm : slbit; -- ibus select hitmiss
65 ibsel_ls : slbit; -- ibus select losize
66 ibsel_nn : slbit; -- ibus select others
67 hm_data : slv6; -- hit/miss: data
68 cr_frep : slv2; -- cntl: force replacement bits
69 cr_fmiss : slv2; -- cntl: force miss bits
70 cr_disutrap: slbit; -- cntl: disable unibus trap
71 cr_distrap: slbit; -- cntl: disable traps
72 end record regs_type;
73
74 constant regs_init : regs_type := (
75 '0','0','0','0', -- ibsel_*
76 (others=>'0'), -- hm_data
77 "00","00", -- cr_frep,_fmiss
78 '0','0' -- dis(u)trap
79 );
80
83
84begin
85
86 proc_regs: process (CLK)
87 begin
88 if rising_edge(CLK) then
89 if CRESET = '1' then
91 else
92 R_REGS <= N_REGS;
93 end if;
94 end if;
95 end process proc_regs;
96
97 proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
98 variable r : regs_type := regs_init;
99 variable n : regs_type := regs_init;
100 variable idout : slv16 := (others=>'0');
101 variable ibreq : slbit := '0';
102 variable ibw0 : slbit := '0';
103 begin
104
105 r := R_REGS;
106 n := R_REGS;
107
108 idout := (others=>'0');
109 ibreq := IB_MREQ.re or IB_MREQ.we;
110 ibw0 := IB_MREQ.we and IB_MREQ.be0;
111
112 -- ibus address decoder
113 n.ibsel_cr := '0';
114 n.ibsel_hm := '0';
115 n.ibsel_ls := '0';
116 n.ibsel_nn := '0';
117 if IB_MREQ.aval = '1' then
118 if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
119 n.ibsel_cr := '1';
120 end if;
121 if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
122 n.ibsel_hm := '1';
123 end if;
124 if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
125 n.ibsel_ls := '1';
126 end if;
127 if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
128 IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
129 IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
130 IB_MREQ.addr=ibaddr_maint(12 downto 1) or
131 IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
132 n.ibsel_nn := '1';
133 end if;
134 end if;
135
136 -- ibus transactions
137 if r.ibsel_cr = '1' then
138 idout(cntl_ibf_frep) := r.cr_frep;
139 idout(cntl_ibf_fmiss) := r.cr_fmiss;
140 idout(cntl_ibf_disutrap) := r.cr_disutrap;
141 idout(cntl_ibf_distrap) := r.cr_distrap;
142 end if;
143 if r.ibsel_hm = '1' then
144 idout(r.hm_data'range) := r.hm_data;
145 end if;
146 if r.ibsel_ls = '1' then
147 idout := slv(to_unsigned(sys_conf_mem_losize,16));
148 end if;
149
150 if r.ibsel_cr='1' and ibw0='1' then
151 n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
152 n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
153 n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
154 n.cr_distrap := IB_MREQ.din(cntl_ibf_distrap);
155 end if;
156
157 if HM_ENA = '1' then
158 n.hm_data := r.hm_data(r.hm_data'left-1 downto 0) & HM_VAL;
159 end if;
160
161 N_REGS <= n;
162
163 IB_SRES.dout <= idout;
164 IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
165 r.ibsel_ls or r.ibsel_nn) and ibreq;
166 IB_SRES.busy <= '0';
167
168 end process proc_next;
169
170 CACHE_FMISS <= (R_REGS.cr_fmiss(1) or R_REGS.cr_fmiss(0));
171
172end syn;
Definition: iblib.vhd:33
slv16 := slv( to_unsigned( 8#177762#, 16) ) ibaddr_hisize
Definition: pdp11_mem70.vhd:55
integer range 5 downto 4 cntl_ibf_frep
Definition: pdp11_mem70.vhd:57
regs_type :=( '0', '0', '0', '0',( others => '0'), "00", "00", '0', '0') regs_init
Definition: pdp11_mem70.vhd:74
slv16 := slv( to_unsigned( 8#177744#, 16) ) ibaddr_syserr
Definition: pdp11_mem70.vhd:50
slv16 := slv( to_unsigned( 8#177740#, 16) ) ibaddr_loaddr
Definition: pdp11_mem70.vhd:48
regs_type := regs_init N_REGS
Definition: pdp11_mem70.vhd:82
integer := 1 cntl_ibf_disutrap
Definition: pdp11_mem70.vhd:59
integer range 3 downto 2 cntl_ibf_fmiss
Definition: pdp11_mem70.vhd:58
slv16 := slv( to_unsigned( 8#177750#, 16) ) ibaddr_maint
Definition: pdp11_mem70.vhd:52
regs_type := regs_init R_REGS
Definition: pdp11_mem70.vhd:81
slv16 := slv( to_unsigned( 8#177752#, 16) ) ibaddr_hm
Definition: pdp11_mem70.vhd:53
integer := 0 cntl_ibf_distrap
Definition: pdp11_mem70.vhd:60
slv16 := slv( to_unsigned( 8#177760#, 16) ) ibaddr_losize
Definition: pdp11_mem70.vhd:54
slv16 := slv( to_unsigned( 8#177746#, 16) ) ibaddr_cntl
Definition: pdp11_mem70.vhd:51
slv16 := slv( to_unsigned( 8#177742#, 16) ) ibaddr_hiaddr
Definition: pdp11_mem70.vhd:49
in HM_ENA slbit
Definition: pdp11_mem70.vhd:38
in CLK slbit
Definition: pdp11_mem70.vhd:36
in HM_VAL slbit
Definition: pdp11_mem70.vhd:39
in CRESET slbit
Definition: pdp11_mem70.vhd:37
in IB_MREQ ib_mreq_type
Definition: pdp11_mem70.vhd:41
out CACHE_FMISS slbit
Definition: pdp11_mem70.vhd:40
out IB_SRES ib_sres_type
Definition: pdp11_mem70.vhd:43
Definition: pdp11.vhd:123
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 5 downto 0) slv6
Definition: slvtypes.vhd:38
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31