w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
rb_mon_sb.vhd
Go to the documentation of this file.
1-- $Id: rb_mon_sb.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rb_mon_sb - sim
7-- Description: simbus wrapper for rbus monitor (for tb's)
8--
9-- Dependencies: simbus
10-- simlib/simclkcnt
11-- rb_mon
12-- Test bench: -
13-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2014-08-28 588 4.0 use new rlink v4 iface and 4 bit STAT
18-- 2011-12-23 444 3.1 use simclkcnt instead of simbus global
19-- 2010-12-22 346 3.0 renamed rritb_rbmon_sb -> rb_mon_sb
20-- 2010-06-05 301 2.0.2 renamed _rpmon -> _rbmon
21-- 2010-05-02 287 2.0.1 rename RP_STAT->RB_STAT,AP_LAM->RB_LAM
22-- drop RP_IINT signal from interfaces
23-- use sbcntl_sbf_cpmon def
24-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
25-- 2007-12-23 105 1.2 added AP_LAM display
26-- 2007-11-24 98 1.1 added RP_IINT support
27-- 2007-08-27 76 1.0 Initial version
28------------------------------------------------------------------------------
29
30library ieee;
31use ieee.std_logic_1164.all;
32
33use work.slvtypes.all;
34use work.simlib.all;
35use work.simbus.all;
36use work.rblib.all;
37
38entity rb_mon_sb is -- simbus wrapper for rbus monitor
39 generic (
40 DBASE : positive := 2; -- base for writing data values
41 ENAPIN : integer := sbcntl_sbf_rbmon); -- SB_CNTL signal to use for enable
42 port (
43 CLK : in slbit; -- clock
44 RB_MREQ : in rb_mreq_type; -- rbus: request
45 RB_SRES : in rb_sres_type; -- rbus: response
46 RB_LAM : in slv16 := (others=>'0'); -- rbus: look at me
47 RB_STAT : in slv4 -- rbus: status flags
48 );
49end rb_mon_sb;
50
51
52architecture sim of rb_mon_sb is
53
54 signal ENA : slbit := '0';
55 signal CLK_CYCLE : integer := 0;
56
57begin
58
59 assert ENAPIN>=SB_CNTL'low and ENAPIN<=SB_CNTL'high
60 report "assert(ENAPIN in SB_CNTL'range)" severity failure;
61
62 CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
63
64 ENA <= to_x01(SB_CNTL(ENAPIN));
65
66 RBMON : rb_mon
67 generic map (
68 DBASE => DBASE)
69 port map (
70 CLK => CLK,
72 ENA => ENA,
75 RB_LAM => RB_LAM,
77 );
78
79end sim;
slbit := '0' ENA
Definition: rb_mon_sb.vhd:54
integer := 0 CLK_CYCLE
Definition: rb_mon_sb.vhd:55
DBASE positive := 2
Definition: rb_mon_sb.vhd:40
in CLK slbit
Definition: rb_mon_sb.vhd:43
in RB_MREQ rb_mreq_type
Definition: rb_mon_sb.vhd:44
ENAPIN integer := sbcntl_sbf_rbmon
Definition: rb_mon_sb.vhd:41
in RB_STAT slv4
Definition: rb_mon_sb.vhd:48
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon_sb.vhd:46
in RB_SRES rb_sres_type
Definition: rb_mon_sb.vhd:45
DBASE positive := 2
Definition: rb_mon.vhd:46
in CLK slbit
Definition: rb_mon.vhd:48
in RB_MREQ rb_mreq_type
Definition: rb_mon.vhd:51
in CLK_CYCLE integer := 0
Definition: rb_mon.vhd:49
in ENA slbit := '1'
Definition: rb_mon.vhd:50
in RB_STAT slv4
Definition: rb_mon.vhd:55
in RB_LAM slv16 :=( others => '0')
Definition: rb_mon.vhd:53
in RB_SRES rb_sres_type
Definition: rb_mon.vhd:52
Definition: rblib.vhd:32
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30