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W11 CPU core and support modules
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rb_sel.vhd
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-- $Id: rb_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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------------------------------------------------------------------------------
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-- Module Name: rb_sel - syn
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-- Description: rbus: address select logic
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--
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-- Dependencies: -
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-- Test bench: -
11
-- Target Devices: generic
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-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2016-04-02 758 4.1 streamline code
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-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
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-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel)
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------------------------------------------------------------------------------
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library
ieee
;
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use
ieee.std_logic_1164.
all
;
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use
work.
slvtypes
.
all
;
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use
work.
rblib
.
all
;
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-- ----------------------------------------------------------------------------
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entity
rb_sel
is
-- rbus address select logic
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generic
(
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RB_ADDR
:
slv16
;
-- rbus address base
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SAWIDTH
:
natural
:=
0
)
;
-- device subaddress space width
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port
(
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CLK
:
in
slbit
;
-- clock
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RB_MREQ
:
in
rb_mreq_type
;
-- ibus request
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SEL
:
out
slbit
-- select state bit
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)
;
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end
rb_sel
;
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architecture
syn
of
rb_sel
is
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signal
R_SEL
:
slbit
:=
'
0
'
;
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begin
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assert
SAWIDTH
<=
15
-- at most 32k word devices
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report
"assert(SAWIDTH<=15)"
severity
failure
;
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proc_regs:
process
(
CLK
)
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begin
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if
rising_edge
(
CLK
)
then
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if
RB_MREQ
.
aval
=
'
1
'
and
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RB_MREQ
.
addr
(
15
downto
SAWIDTH
)
=
RB_ADDR
(
15
downto
SAWIDTH
)
then
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R_SEL
<=
'
1
'
;
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else
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R_SEL
<=
'
0
'
;
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end
if
;
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end
if
;
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end
process
proc_regs
;
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SEL
<=
R_SEL
;
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end
syn;
rb_sel.syn
Definition:
rb_sel.vhd:40
rb_sel.syn.R_SEL
slbit := '0' R_SEL
Definition:
rb_sel.vhd:41
rb_sel
Definition:
rb_sel.vhd:29
rb_sel.SEL
out SEL slbit
Definition:
rb_sel.vhd:37
rb_sel.SAWIDTH
SAWIDTH natural := 0
Definition:
rb_sel.vhd:32
rb_sel.CLK
in CLK slbit
Definition:
rb_sel.vhd:34
rb_sel.RB_MREQ
in RB_MREQ rb_mreq_type
Definition:
rb_sel.vhd:35
rb_sel.RB_ADDR
RB_ADDR slv16
Definition:
rb_sel.vhd:31
rblib
Definition:
rblib.vhd:32
slvtypes
Definition:
slvtypes.vhd:28
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition:
slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition:
slvtypes.vhd:30
vlib
rbus
rb_sel.vhd
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