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W11 CPU core and support modules
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rb_sel.vhd
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1-- $Id: rb_sel.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rb_sel - syn
7-- Description: rbus: address select logic
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2016-04-02 758 4.1 streamline code
17-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
18-- 2010-12-26 349 1.0 Initial version (cloned from ibus/ib_sel)
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23
24use work.slvtypes.all;
25use work.rblib.all;
26
27-- ----------------------------------------------------------------------------
28
29entity rb_sel is -- rbus address select logic
30 generic (
31 RB_ADDR : slv16; -- rbus address base
32 SAWIDTH : natural := 0); -- device subaddress space width
33 port (
34 CLK : in slbit; -- clock
35 RB_MREQ : in rb_mreq_type; -- ibus request
36 SEL : out slbit -- select state bit
37 );
38end rb_sel;
39
40architecture syn of rb_sel is
41 signal R_SEL : slbit := '0';
42begin
43
44 assert SAWIDTH<=15 -- at most 32k word devices
45 report "assert(SAWIDTH<=15)" severity failure;
46
47 proc_regs: process (CLK)
48 begin
49 if rising_edge(CLK) then
50 if RB_MREQ.aval='1' and
51 RB_MREQ.addr(15 downto SAWIDTH)=RB_ADDR(15 downto SAWIDTH) then
52 R_SEL <= '1';
53 else
54 R_SEL <= '0';
55 end if;
56 end if;
57 end process proc_regs;
58
59 SEL <= R_SEL;
60
61end syn;
slbit := '0' R_SEL
Definition: rb_sel.vhd:41
out SEL slbit
Definition: rb_sel.vhd:37
SAWIDTH natural := 0
Definition: rb_sel.vhd:32
in CLK slbit
Definition: rb_sel.vhd:34
in RB_MREQ rb_mreq_type
Definition: rb_sel.vhd:35
RB_ADDR slv16
Definition: rb_sel.vhd:31
Definition: rblib.vhd:32
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30