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W11 CPU core and support modules
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rbd_rbmon.vhd
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1-- $Id: rbd_rbmon.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rbd_rbmon - syn
7-- Description: rbus dev: rbus monitor
8--
9-- Dependencies: memlib/ram_1swsr_wfirst_gen
10--
11-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
12--
13-- Target Devices: generic
14-- Tool versions: xst 12.1-14.7; viv 2014.4-2018.3; ghdl 0.29-0.35
15--
16-- Synthesized (xst):
17-- Date Rev ise Target flop lutl lutm slic t peri
18-- 2017-04-14 873 14.7 131013 xc6slx16-2 124 187 - 67 s 5.9
19-- 2017-04-08 758 14.7 131013 xc6slx16-2 112 200 - 73 s 5.7
20-- 2014-12-22 619 14.7 131013 xc6slx16-2 114 209 - 72 s 5.6
21-- 2014-12-21 593 14.7 131013 xc6slx16-2 99 207 - 77 s 7.0
22-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2019-06-02 1159 6.0.2 use rbaddr_ constants
27-- 2019-03-02 1116 6.0.1 more robust ack,err trace when busy
28-- 2017-04-16 879 6.0 revised interface, add suspend and repeat collapse
29-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue
30-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses
31-- 2014-09-13 593 4.1 change default address -> ffe8
32-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit (but only 8 bit recorded)
33-- 2011-11-19 427 1.0.3 now numeric_std clean
34-- 2011-03-27 374 1.0.2 rename ncyc -> nbusy because it counts busy cycles
35-- 2010-12-31 352 1.0.1 simplify irb_ack logic
36-- 2010-12-27 349 1.0 Initial version
37------------------------------------------------------------------------------
38--
39-- Addr Bits Name r/w/f Function
40-- 000 cntl r/w/f Control register
41-- 05 rcolw r/w/- repeat collapse writes
42-- 04 rcolr r/w/- repeat collapse reads
43-- 03 wstop r/w/- stop on wrap
44-- 02:00 func 0/-/f change run status if != noop
45-- 0xx noop
46-- 100 sto stop
47-- 101 sta start and latch all options
48-- 110 sus suspend (noop if not started)
49-- 111 res resume (noop if not started)
50-- 001 stat r/w/- Status register
51-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
52-- 02 wrap r/-/- line address wrapped (cleared on start)
53-- 01 susp r/-/- suspended
54-- 00 run r/-/- running (can be suspended)
55-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb)
56-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000)
57-- 100 addr r/w/- Address register
58-- *:02 laddr r/w/- line address
59-- 01:00 waddr r/w/- word address
60-- 101 data r/w/- Data register
61--
62-- data format:
63-- word 3 15 : burst (2nd re/we in a aval sequence)
64-- 14 : tout (busy in last re-we cycle)
65-- 13 : nak (no ack in last non-busy cycle)
66-- 12 : ack (ack seen)
67-- 11 : busy (busy seen)
68-- 10 : err (err seen)
69-- 09 : we (write cycle)
70-- 08 : init (init cycle)
71-- 07:00 : delay to prev (msb's)
72-- word 2 15:10 : delay to prev (lsb's)
73-- 09:00 : number of busy cycles
74-- word 1 : data
75-- word 0 : addr
76--
77
78
79library ieee;
80use ieee.std_logic_1164.all;
81use ieee.numeric_std.all;
82
83use work.slvtypes.all;
84use work.memlib.all;
85use work.rblib.all;
86use work.rbdlib.all;
87
88-- Note: AWIDTH has type natural to allow AWIDTH=0 can be used in if generates
89-- to control the instantiation. ghdl checks even for not instantiated
90-- entities the validity of generics, that's why natural needed here ....
91
92entity rbd_rbmon is -- rbus dev: rbus monitor
93 generic (
94 RB_ADDR : slv16 := rbaddr_rbmon;
95 AWIDTH : natural := 9);
96 port (
97 CLK : in slbit; -- clock
98 RESET : in slbit; -- reset
99 RB_MREQ : in rb_mreq_type; -- rbus: request
100 RB_SRES : out rb_sres_type; -- rbus: response
101 RB_SRES_SUM : in rb_sres_type -- rbus: response (sum for monitor)
102 );
103end entity rbd_rbmon;
104
105
106architecture syn of rbd_rbmon is
107
108 constant rbaddr_cntl : slv3 := "000"; -- cntl address offset
109 constant rbaddr_stat : slv3 := "001"; -- stat address offset
110 constant rbaddr_hilim : slv3 := "010"; -- hilim address offset
111 constant rbaddr_lolim : slv3 := "011"; -- lolim address offset
112 constant rbaddr_addr : slv3 := "100"; -- addr address offset
113 constant rbaddr_data : slv3 := "101"; -- data address offset
114
115 constant cntl_rbf_rcolw : integer := 5;
116 constant cntl_rbf_rcolr : integer := 4;
117 constant cntl_rbf_wstop : integer := 3;
118 subtype cntl_rbf_func is integer range 2 downto 0;
119
120 subtype stat_rbf_bsize is integer range 15 downto 13;
121 constant stat_rbf_wrap : integer := 2;
122 constant stat_rbf_susp : integer := 1;
123 constant stat_rbf_run : integer := 0;
124
125 subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2;
126 subtype addr_rbf_waddr is integer range 1 downto 0;
127
128 constant dat3_rbf_burst : integer := 15;
129 constant dat3_rbf_tout : integer := 14;
130 constant dat3_rbf_nak : integer := 13;
131 constant dat3_rbf_ack : integer := 12;
132 constant dat3_rbf_busy : integer := 11;
133 constant dat3_rbf_err : integer := 10;
134 constant dat3_rbf_we : integer := 9;
135 constant dat3_rbf_init : integer := 8;
136 subtype dat3_rbf_ndlymsb is integer range 7 downto 0;
137 subtype dat2_rbf_ndlylsb is integer range 15 downto 10;
138 subtype dat2_rbf_nbusy is integer range 9 downto 0;
139
140 constant func_sto : slv3 := "100"; -- func: stop
141 constant func_sta : slv3 := "101"; -- func: start
142 constant func_sus : slv3 := "110"; -- func: suspend
143 constant func_res : slv3 := "111"; -- func: resume
144
145 type regs_type is record -- state registers
146 rbsel : slbit; -- rbus select
147 rcolw : slbit; -- rcolw flag (repeat collect writes)
148 rcolr : slbit; -- rcolr flag (repeat collect reads)
149 wstop : slbit; -- wstop flag (stop on wrap)
150 susp : slbit; -- suspended flag
151 go : slbit; -- go flag
152 hilim : slv16; -- upper address limit
153 lolim : slv16; -- lower address limit
154 wrap : slbit; -- laddr wrap flag
155 laddr : slv(AWIDTH-1 downto 0); -- line address
156 waddr : slv2; -- word address
157 addrsame: slbit; -- curr rb addr equal last rb addr
158 addrwind: slbit; -- curr rb addr in [lolim,hilim] window
159 aval_1 : slbit; -- last cycle aval
160 arm1r : slbit; -- 1st level arm for read
161 arm2r : slbit; -- 2nd level arm for read
162 arm1w : slbit; -- 1st level arm for write
163 arm2w : slbit; -- 2nd level arm for write
164 rcol : slbit; -- repeat collaps
165 rbtake_1 : slbit; -- rb capture active in last cycle
166 rbaddr : slv16; -- rbus trace: addr
167 rbinit : slbit; -- rbus trace: init
168 rbwe : slbit; -- rbus trace: we
169 rback : slbit; -- rbus trace: ack seen
170 rbbusy : slbit; -- rbus trace: busy seen
171 rberr : slbit; -- rbus trace: err seen
172 rbnak : slbit; -- rbus trace: nak detected
173 rbtout : slbit; -- rbus trace: tout detected
174 rbburst : slbit; -- rbus trace: burst detected
175 rbdata : slv16; -- rbus trace: data
176 rbnbusy : slv10; -- rbus number of busy cycles
177 rbndly : slv14; -- rbus delay to prev. access
178 end record regs_type;
179
180 constant laddrzero : slv(AWIDTH-1 downto 0) := (others=>'0');
181 constant laddrlast : slv(AWIDTH-1 downto 0) := (others=>'1');
182
183 constant regs_init : regs_type := (
184 '0', -- rbsel
185 '0','0','0', -- rcolw,rcolr,wstop
186 '0','1', -- susp,go
187 x"fffb", -- hilim (def: fffb)
188 x"0000", -- lolim (def: 0000)
189 '0', -- wrap
190 laddrzero, -- laddr
191 "00", -- waddr
192 '0','0','0', -- addrsame,addrwind,aval_1
193 '0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
194 '0', -- rbtake_1
195 x"ffff", -- rbaddr (startup: ffff)
196 '0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr
197 '0','0','0', -- rbnak,rbtout,rbburst
198 (others=>'0'), -- rbdata
199 (others=>'0'), -- rbnbusy
200 (others=>'0') -- rbndly
201 );
202
203 constant rbnbusylast : slv10 := (others=>'1');
204 constant rbndlylast : slv14 := (others=>'1');
205
208
209 signal BRAM_EN : slbit := '0';
210 signal BRAM_WE : slbit := '0';
211 signal BRAM0_DI : slv32 := (others=>'0');
212 signal BRAM1_DI : slv32 := (others=>'0');
213 signal BRAM0_DO : slv32 := (others=>'0');
214 signal BRAM1_DO : slv32 := (others=>'0');
215 signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
216
217begin
218
219 assert AWIDTH>=9 and AWIDTH<=14
220 report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
221 severity failure;
222
224 generic map (
225 AWIDTH => AWIDTH,
226 DWIDTH => 32)
227 port map (
228 CLK => CLK,
229 EN => BRAM_EN,
230 WE => BRAM_WE,
231 ADDR => BRAM_ADDR,
232 DI => BRAM1_DI,
233 DO => BRAM1_DO
234 );
235
237 generic map (
238 AWIDTH => AWIDTH,
239 DWIDTH => 32)
240 port map (
241 CLK => CLK,
242 EN => BRAM_EN,
243 WE => BRAM_WE,
244 ADDR => BRAM_ADDR,
245 DI => BRAM0_DI,
246 DO => BRAM0_DO
247 );
248
249 proc_regs: process (CLK)
250 begin
251 if rising_edge(CLK) then
252 if RESET = '1' then
253 R_REGS <= regs_init;
254 else
255 R_REGS <= N_REGS;
256 end if;
257 end if;
258 end process proc_regs;
259
260 proc_next : process (R_REGS, RB_MREQ, RB_SRES_SUM, BRAM0_DO, BRAM1_DO)
261 variable r : regs_type := regs_init;
262 variable n : regs_type := regs_init;
263 variable irb_ack : slbit := '0';
264 variable irb_busy : slbit := '0';
265 variable irb_err : slbit := '0';
266 variable irb_dout : slv16 := (others=>'0');
267 variable irbena : slbit := '0';
268 variable ibramen : slbit := '0'; -- BRAM enable
269 variable ibramwe : slbit := '0'; -- BRAN we
270 variable rbtake : slbit := '0';
271 variable laddr_inc : slbit := '0';
272 variable idat0 : slv16 := (others=>'0');
273 variable idat1 : slv16 := (others=>'0');
274 variable idat2 : slv16 := (others=>'0');
275 variable idat3 : slv16 := (others=>'0');
276 variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
277 variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
278 begin
279
280 r := R_REGS;
281 n := R_REGS;
282
283 irb_ack := '0';
284 irb_busy := '0';
285 irb_err := '0';
286 irb_dout := (others=>'0');
287
288 irbena := RB_MREQ.re or RB_MREQ.we;
289
290 ibramen := '0';
291 ibramwe := '0';
292
293 laddr_inc := '0';
294
295 -- rbus address decoder
296 n.rbsel := '0';
297 if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 3)=RB_ADDR(15 downto 3) then
298 n.rbsel := '1';
299 ibramen := '1';
300 end if;
301
302 -- rbus transactions
303 if r.rbsel = '1' then
304
305 irb_ack := irbena; -- ack all accesses
306
307 case RB_MREQ.addr(2 downto 0) is
308
309 when rbaddr_cntl => -- cntl ------------------
310 if RB_MREQ.we = '1' then
311 case RB_MREQ.din(cntl_rbf_func) is
312 when func_sto => -- func: stop ------------
313 n.go := '0';
314 n.susp := '0';
315 when func_sta => -- func: start -----------
316 n.rcolw := RB_MREQ.din(cntl_rbf_rcolw);
317 n.rcolr := RB_MREQ.din(cntl_rbf_rcolr);
318 n.wstop := RB_MREQ.din(cntl_rbf_wstop);
319 n.go := '1';
320 n.susp := '0';
321 n.wrap := '0';
322 n.laddr := laddrzero;
323 n.waddr := "00";
324 when func_sus => -- func: susp ------------
325 if r.go = '1' then -- noop unless running
326 n.go := '0';
327 n.susp := r.go;
328 end if;
329 when func_res => -- func: resu ------------
330 n.go := r.susp;
331 n.susp := '0';
332 when others => null; -- <> --------------------
333 end case;
334 end if;
335
336 when rbaddr_stat => null; -- stat ------------------
337
338 when rbaddr_hilim => -- hilim -----------------
339 if RB_MREQ.we = '1' then
340 n.hilim := RB_MREQ.din;
341 end if;
342
343 when rbaddr_lolim => -- lolim -----------------
344 if RB_MREQ.we = '1' then
345 n.lolim := RB_MREQ.din;
346 end if;
347
348 when rbaddr_addr => -- addr ------------------
349 if RB_MREQ.we = '1' then
350 if r.go = '0' then -- if not active OK
351 n.laddr := RB_MREQ.din(addr_rbf_laddr);
352 n.waddr := RB_MREQ.din(addr_rbf_waddr);
353 else
354 irb_err := '1'; -- otherwise error
355 end if;
356 end if;
357
358 when rbaddr_data => -- data ------------------
359 -- write to data is an error
360 if RB_MREQ.we='1' then
361 irb_err := '1';
362 end if;
363 -- read to data always allowed, addr only incremented when not active
364 if RB_MREQ.re = '1' and r.go = '0' then
365 n.waddr := slv(unsigned(r.waddr) + 1);
366 if r.waddr = "11" then
367 laddr_inc := '1';
368 end if;
369 end if;
370
371 when others => -- <> --------------------
372 irb_err := '1';
373
374 end case;
375 end if;
376
377 -- rbus output driver
378 if r.rbsel = '1' then
379 case RB_MREQ.addr(2 downto 0) is
380 when rbaddr_cntl => -- cntl ------------------
381 irb_dout(cntl_rbf_rcolw) := r.rcolw;
382 irb_dout(cntl_rbf_rcolr) := r.rcolr;
383 irb_dout(cntl_rbf_wstop) := r.wstop;
384 when rbaddr_stat => -- stat ------------------
385 irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-9,3));
386 irb_dout(stat_rbf_wrap) := r.wrap;
387 irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
388 irb_dout(stat_rbf_run) := r.go or r.susp; -- started
389 when rbaddr_hilim => -- hilim -----------------
390 irb_dout := r.hilim;
391 when rbaddr_lolim => -- lolim -----------------
392 irb_dout := r.lolim;
393 when rbaddr_addr => -- addr ------------------
394 irb_dout(addr_rbf_laddr) := r.laddr;
395 irb_dout(addr_rbf_waddr) := r.waddr;
396 when rbaddr_data => -- data ------------------
397 case r.waddr is
398 when "11" => irb_dout := BRAM1_DO(31 downto 16);
399 when "10" => irb_dout := BRAM1_DO(15 downto 0);
400 when "01" => irb_dout := BRAM0_DO(31 downto 16);
401 when "00" => irb_dout := BRAM0_DO(15 downto 0);
402 when others => null;
403 end case;
404 when others => null;
405 end case;
406 end if;
407
408 -- rbus monitor
409 -- a rbus transaction are captured if the address is in alim window
410 -- and the access is not refering to rbd_rbmon itself
411 -- Note: rbus init cycles come with aval=0 but addr is valid and checked !
412
413 -- rbus address monitor
414 if (RB_MREQ.aval='1' and r.aval_1='0') or RB_MREQ.init='1' then
415 n.rbaddr := RB_MREQ.addr;
416 n.addrsame := '0';
417 if RB_MREQ.addr = r.rbaddr then
418 n.addrsame := '1';
419 end if;
420 n.addrwind := '0';
421 if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
422 unsigned(RB_MREQ.addr)<=unsigned(r.hilim) then
423 n.addrwind := '1';
424 end if;
425 end if;
426 n.aval_1 := RB_MREQ.aval;
427
428 -- rbus data monitor
429 if (RB_MREQ.aval='1' and irbena='1') or RB_MREQ.init='1' then
430 if RB_MREQ.init='1' or RB_MREQ.we='1' then -- for write/init of din
431 n.rbdata := RB_MREQ.din;
432 else -- for read of dout
433 n.rbdata := RB_SRES_SUM.dout;
434 end if;
435 end if;
436
437 -- track state and decide on storage
438 rbtake := '0';
439 if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
440 if r.addrwind='1' and r.rbsel='0' then -- and in window and not self
441 rbtake := '1';
442 end if;
443 end if;
444 if RB_MREQ.init = '1' then -- also take init's
445 rbtake := '1';
446 end if;
447
448 if rbtake = '1' then -- if capture active
449 n.rbinit := RB_MREQ.init; -- keep track of some state
450 n.rbwe := RB_MREQ.we;
451
452 if r.rbtake_1 = '0' then -- if initial cycle of a transaction
453 n.rback := RB_SRES_SUM.ack;
454 n.rbbusy := RB_SRES_SUM.busy;
455 n.rberr := RB_SRES_SUM.err;
456 n.rbnbusy := (others=>'0');
457 else -- if non-initial cycles
458 n.rback := r.rback or RB_SRES_SUM.ack; -- keep track of ack
459 n.rberr := r.rberr or RB_SRES_SUM.err; -- keep track of err
460 if r.rbnbusy /= rbnbusylast then -- and count
461 n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
462 end if;
463 end if;
464 n.rbnak := not RB_SRES_SUM.ack;
465 n.rbtout := RB_SRES_SUM.busy;
466
467 if RB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
468 n.addrsame := '1'; -- in case of burst
469 n.arm1r := r.rcolr and RB_MREQ.re;
470 n.arm1w := r.rcolw and RB_MREQ.we;
471 n.arm2r := r.arm1r and r.addrsame and RB_MREQ.re;
472 n.arm2w := r.arm1w and r.addrsame and RB_MREQ.we;
473 n.rcol := ((r.arm2r and RB_MREQ.re) or
474 (r.arm2w and RB_MREQ.we)) and r.addrsame;
475 end if;
476
477 else -- if capture not active
478 if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended
479 ibramen := '1';
480 ibramwe := '1';
481 laddr_inc := '1';
482 n.rbburst := '1'; -- assume burst
483 end if;
484 if r.rbtake_1 = '1' then -- rbus transaction just ended
485 n.rbndly := (others=>'0'); -- clear delay counter
486 else -- just idle
487 if r.rbndly /= rbndlylast then -- count cycles
488 n.rbndly := slv(unsigned(r.rbndly) + 1);
489 end if;
490 end if;
491 end if;
492
493 if RB_MREQ.aval = '0' then -- if aval gone
494 n.rbburst := '0'; -- clear burst flag
495 end if;
496
497 iaddrinc := (others=>'0');
498 iaddroff := (others=>'0');
499 iaddrinc(0) := not (r.rcol and r.go);
500 iaddroff(0) := (r.rcol and r.go);
501
502 if laddr_inc = '1' then
503 n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
504 if r.go='1' and r.laddr=laddrlast then
505 n.wrap := '1';
506 if r.wstop = '1' then
507 n.go := '0';
508 end if;
509 end if;
510 end if;
511
512 idat3 := (others=>'0');
513 idat3(dat3_rbf_burst) := r.rbburst;
514 idat3(dat3_rbf_tout) := r.rbtout;
515 idat3(dat3_rbf_nak) := r.rbnak;
516 idat3(dat3_rbf_ack) := r.rback;
517 idat3(dat3_rbf_busy) := r.rbbusy;
518 idat3(dat3_rbf_err) := r.rberr;
519 idat3(dat3_rbf_we) := r.rbwe;
520 idat3(dat3_rbf_init) := r.rbinit;
521 idat3(dat3_rbf_ndlymsb):= r.rbndly(13 downto 6);
522 idat2(dat2_rbf_ndlylsb):= r.rbndly( 5 downto 0);
523 idat2(dat2_rbf_nbusy) := r.rbnbusy;
524 idat1 := r.rbdata;
525 idat0 := r.rbaddr;
526
527 n.rbtake_1 := rbtake;
528
529 N_REGS <= n;
530
531 BRAM_EN <= ibramen;
532 BRAM_WE <= ibramwe;
533 BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
534
535 BRAM1_DI <= idat3 & idat2;
536 BRAM0_DI <= idat1 & idat0;
537
538 RB_SRES.dout <= irb_dout;
539 RB_SRES.ack <= irb_ack;
540 RB_SRES.err <= irb_err;
541 RB_SRES.busy <= irb_busy;
542
543 end process proc_next;
544
545end syn;
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
slv3 := "100" func_sto
Definition: rbd_rbmon.vhd:140
slv3 := "011" rbaddr_lolim
Definition: rbd_rbmon.vhd:111
integer range 1 downto 0 addr_rbf_waddr
Definition: rbd_rbmon.vhd:126
slbit := '0' BRAM_EN
Definition: rbd_rbmon.vhd:209
integer := 2 stat_rbf_wrap
Definition: rbd_rbmon.vhd:121
integer := 8 dat3_rbf_init
Definition: rbd_rbmon.vhd:135
integer := 9 dat3_rbf_we
Definition: rbd_rbmon.vhd:134
integer := 5 cntl_rbf_rcolw
Definition: rbd_rbmon.vhd:115
regs_type := regs_init N_REGS
Definition: rbd_rbmon.vhd:207
regs_type :=( '0', '0', '0', '0', '0', '1', x"fffb", x"0000", '0', laddrzero, "00", '0', '0', '0', '0', '0', '0', '0', '0', '0', x"ffff", '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'),( others => '0')) regs_init
Definition: rbd_rbmon.vhd:183
slv3 := "101" func_sta
Definition: rbd_rbmon.vhd:141
slv3 := "101" rbaddr_data
Definition: rbd_rbmon.vhd:113
integer := 11 dat3_rbf_busy
Definition: rbd_rbmon.vhd:132
integer range 7 downto 0 dat3_rbf_ndlymsb
Definition: rbd_rbmon.vhd:136
slbit := '0' BRAM_WE
Definition: rbd_rbmon.vhd:210
slv32 :=( others => '0') BRAM0_DI
Definition: rbd_rbmon.vhd:211
integer range 2+ AWIDTH- 1 downto 2 addr_rbf_laddr
Definition: rbd_rbmon.vhd:125
slv3 := "000" rbaddr_cntl
Definition: rbd_rbmon.vhd:108
integer := 12 dat3_rbf_ack
Definition: rbd_rbmon.vhd:131
slv3 := "001" rbaddr_stat
Definition: rbd_rbmon.vhd:109
slv32 :=( others => '0') BRAM1_DI
Definition: rbd_rbmon.vhd:212
integer range 2 downto 0 cntl_rbf_func
Definition: rbd_rbmon.vhd:118
slv14 :=( others => '1') rbndlylast
Definition: rbd_rbmon.vhd:204
slv( AWIDTH- 1 downto 0) :=( others => '1') laddrlast
Definition: rbd_rbmon.vhd:181
integer := 4 cntl_rbf_rcolr
Definition: rbd_rbmon.vhd:116
regs_type := regs_init R_REGS
Definition: rbd_rbmon.vhd:206
integer := 3 cntl_rbf_wstop
Definition: rbd_rbmon.vhd:117
slv( AWIDTH- 1 downto 0) :=( others => '0') BRAM_ADDR
Definition: rbd_rbmon.vhd:215
slv3 := "010" rbaddr_hilim
Definition: rbd_rbmon.vhd:110
integer := 15 dat3_rbf_burst
Definition: rbd_rbmon.vhd:128
integer := 1 stat_rbf_susp
Definition: rbd_rbmon.vhd:122
integer := 14 dat3_rbf_tout
Definition: rbd_rbmon.vhd:129
integer := 10 dat3_rbf_err
Definition: rbd_rbmon.vhd:133
slv32 :=( others => '0') BRAM1_DO
Definition: rbd_rbmon.vhd:214
integer := 13 dat3_rbf_nak
Definition: rbd_rbmon.vhd:130
slv3 := "111" func_res
Definition: rbd_rbmon.vhd:143
integer range 15 downto 13 stat_rbf_bsize
Definition: rbd_rbmon.vhd:120
slv3 := "110" func_sus
Definition: rbd_rbmon.vhd:142
slv3 := "100" rbaddr_addr
Definition: rbd_rbmon.vhd:112
slv32 :=( others => '0') BRAM0_DO
Definition: rbd_rbmon.vhd:213
integer range 15 downto 10 dat2_rbf_ndlylsb
Definition: rbd_rbmon.vhd:137
integer range 9 downto 0 dat2_rbf_nbusy
Definition: rbd_rbmon.vhd:138
slv( AWIDTH- 1 downto 0) :=( others => '0') laddrzero
Definition: rbd_rbmon.vhd:180
integer := 0 stat_rbf_run
Definition: rbd_rbmon.vhd:123
slv10 :=( others => '1') rbnbusylast
Definition: rbd_rbmon.vhd:203
in RESET slbit
Definition: rbd_rbmon.vhd:98
RB_ADDR slv16 := rbaddr_rbmon
Definition: rbd_rbmon.vhd:94
AWIDTH natural := 9
Definition: rbd_rbmon.vhd:95
in CLK slbit
Definition: rbd_rbmon.vhd:97
in RB_MREQ rb_mreq_type
Definition: rbd_rbmon.vhd:99
out RB_SRES rb_sres_type
Definition: rbd_rbmon.vhd:100
in RB_SRES_SUM rb_sres_type
Definition: rbd_rbmon.vhd:102
Definition: rblib.vhd:32
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 9 downto 0) slv10
Definition: slvtypes.vhd:42
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31