80use ieee.std_logic_1164.
all;
81use ieee.numeric_std.
all;
220 report "assert(AWIDTH>=9 and AWIDTH<=14): unsupported AWIDTH"
251 if rising_edge(CLK) then
258 end process proc_regs;
263 variable irb_ack : slbit := '0';
264 variable irb_busy : slbit := '0';
265 variable irb_err : slbit := '0';
266 variable irb_dout : slv16 := (others=>'0');
267 variable irbena : slbit := '0';
268 variable ibramen : slbit := '0';
269 variable ibramwe : slbit := '0';
270 variable rbtake : slbit := '0';
271 variable laddr_inc : slbit := '0';
272 variable idat0 : slv16 := (others=>'0');
273 variable idat1 : slv16 := (others=>'0');
274 variable idat2 : slv16 := (others=>'0');
275 variable idat3 : slv16 := (others=>'0');
276 variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
277 variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
286 irb_dout := (others=>'0');
303 if r.rbsel = '1' then
307 case RB_MREQ.addr(2 downto 0) is
364 if RB_MREQ.re = '1' and r.go = '0' then
365 n.waddr := slv(unsigned(r.waddr) + 1);
366 if r.waddr = "11" then
378 if r.rbsel = '1' then
379 case RB_MREQ.addr(2 downto 0) is
398 when "11" => irb_dout := BRAM1_DO(31 downto 16);
399 when "10" => irb_dout := BRAM1_DO(15 downto 0);
400 when "01" => irb_dout := BRAM0_DO(31 downto 16);
401 when "00" => irb_dout := BRAM0_DO(15 downto 0);
417 if RB_MREQ.addr = r.rbaddr then
421 if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and
422 unsigned(RB_MREQ.addr)<=unsigned(r.hilim) then
439 if RB_MREQ.aval='1' and irbena='1' then
440 if r.addrwind='1' and r.rbsel='0' then
452 if r.rbtake_1 = '0' then
456 n.rbnbusy := (others=>'0');
461 n.rbnbusy := slv(unsigned(r.rbnbusy) + 1);
469 n.arm1r := r.rcolr and RB_MREQ.re;
470 n.arm1w := r.rcolw and RB_MREQ.we;
471 n.arm2r := r.arm1r and r.addrsame and RB_MREQ.re;
472 n.arm2w := r.arm1w and r.addrsame and RB_MREQ.we;
473 n.rcol := ((r.arm2r and RB_MREQ.re) or
474 (r.arm2w and RB_MREQ.we)) and r.addrsame;
478 if r.go='1' and r.rbtake_1='1' then
484 if r.rbtake_1 = '1' then
485 n.rbndly := (others=>'0');
488 n.rbndly := slv(unsigned(r.rbndly) + 1);
497 iaddrinc := (others=>'0');
498 iaddroff := (others=>'0');
499 iaddrinc(0) := not (r.rcol and r.go);
500 iaddroff(0) := (r.rcol and r.go);
502 if laddr_inc = '1' then
503 n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
506 if r.wstop = '1' then
512 idat3 := (others=>'0');
527 n.rbtake_1 := rbtake;
543 end process proc_next;
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
slv3 := "011" rbaddr_lolim
integer range 1 downto 0 addr_rbf_waddr
integer := 2 stat_rbf_wrap
integer := 8 dat3_rbf_init
integer := 5 cntl_rbf_rcolw
regs_type := regs_init N_REGS
regs_type :=( '0', '0', '0', '0', '0', '1', x"fffb", x"0000", '0', laddrzero, "00", '0', '0', '0', '0', '0', '0', '0', '0', '0', x"ffff", '0', '0', '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'),( others => '0')) regs_init
slv3 := "101" rbaddr_data
integer := 11 dat3_rbf_busy
integer range 7 downto 0 dat3_rbf_ndlymsb
slv32 :=( others => '0') BRAM0_DI
integer range 2+ AWIDTH- 1 downto 2 addr_rbf_laddr
slv3 := "000" rbaddr_cntl
integer := 12 dat3_rbf_ack
slv3 := "001" rbaddr_stat
slv32 :=( others => '0') BRAM1_DI
integer range 2 downto 0 cntl_rbf_func
slv14 :=( others => '1') rbndlylast
slv( AWIDTH- 1 downto 0) :=( others => '1') laddrlast
integer := 4 cntl_rbf_rcolr
regs_type := regs_init R_REGS
integer := 3 cntl_rbf_wstop
slv( AWIDTH- 1 downto 0) :=( others => '0') BRAM_ADDR
slv3 := "010" rbaddr_hilim
integer := 15 dat3_rbf_burst
integer := 1 stat_rbf_susp
integer := 14 dat3_rbf_tout
integer := 10 dat3_rbf_err
slv32 :=( others => '0') BRAM1_DO
integer := 13 dat3_rbf_nak
integer range 15 downto 13 stat_rbf_bsize
slv3 := "100" rbaddr_addr
slv32 :=( others => '0') BRAM0_DO
integer range 15 downto 10 dat2_rbf_ndlylsb
integer range 9 downto 0 dat2_rbf_nbusy
slv( AWIDTH- 1 downto 0) :=( others => '0') laddrzero
integer := 0 stat_rbf_run
slv10 :=( others => '1') rbnbusylast
RB_ADDR slv16 := rbaddr_rbmon
in RB_SRES_SUM rb_sres_type
std_logic_vector( 13 downto 0) slv14
std_logic_vector( 9 downto 0) slv10
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 1 downto 0) slv2