w11 - vhd 0.794
W11 CPU core and support modules
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rlink_mon.vhd
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1-- $Id: rlink_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rlink_mon - sim
7-- Description: rlink monitor (for tb's)
8--
9-- Dependencies: -
10-- Test bench: -
11-- Tool versions: xst 8.2-17.7; ghdl 0.18-0.31
12--
13-- Revision History:
14-- Date Rev Version Comment
15-- 2014-11-08 602 4.0.2 annotate clobber commas
16-- 2014-10-25 599 4.0.1 use writeoptint()
17-- 2014-10-12 596 4.0 adopt to new escaping, better 8 bit output
18-- 2011-12-23 444 3.1 CLK_CYCLE now integer
19-- 2011-11-19 427 3.0.2 now numeric_std clean
20-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
21-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
22-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
23-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
24-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
25-- 2007-09-09 81 1.0 Initial version
26------------------------------------------------------------------------------
27
28library ieee;
29use ieee.std_logic_1164.all;
30use ieee.numeric_std.all;
31use ieee.std_logic_textio.all;
32use std.textio.all;
33
34use work.slvtypes.all;
35use work.simlib.all;
36use work.rlinklib.all;
37use work.comlib.all;
38
39entity rlink_mon is -- rlink monitor
40 generic (
41 DWIDTH : positive := 9); -- data port width (8 or 9)
42 port (
43 CLK : in slbit; -- clock
44 CLK_CYCLE : in integer := 0; -- clock cycle number
45 ENA : in slbit := '1'; -- enable monitor output
46 RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
47 RL_ENA : in slbit; -- rlink: data enable
48 RL_BUSY : in slbit; -- rlink: data busy
49 RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
50 RL_VAL : in slbit; -- rlink: data valid
51 RL_HOLD : in slbit -- rlink: data hold
52 );
53end rlink_mon;
54
55
56architecture sim of rlink_mon is
57
58begin
59
60 assert DWIDTH=8 or DWIDTH=9
61 report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
62
63 proc_moni: process
64 variable oline : line;
65 variable nbusy : integer := 0;
66 variable nhold : integer := 0;
67 variable edatarx : boolean := false;
68 variable edatatx : boolean := false;
69
70- procedure write_val(L: inout line;
71 data: in slv(DWIDTH1 downto 0);
72 nwait: in integer;
73 txt1: in string(1 to 2);
74 txt2: in string;
75 edata: in boolean) is
76 variable data9 : slv9 := (others=>'0');
77 variable optxt : string(1 to 8) := ": ??rx ";
78 begin
79
80 if DWIDTH = 9 then
81 optxt(3 to 4) := "rl";
82 else
83 optxt(3 to 4) := "r8";
84 end if;
85 optxt(5 to 6) := txt1;
86 writetimestamp(L, CLK_CYCLE, optxt);
87
88 if DWIDTH = 9 then
89 write(L, data(data'left), right, 1);
90 else
91 write(L, string'(" "));
92 end if;
93
94 write(L, data(7 downto 0), right, 9);
95 writeoptint(L, txt2, nwait);
96
97 if DWIDTH=9 and data(data'left)='1' then
98 -- a copy to data9 needed to allow following case construct
99 -- using data directly gives a 'subtype is not locally static' error
100 data9 := (others=>'0');
101 data9(data'range) := data;
102 write(L, string'(" comma"));
103 case data9 is
104 when c_rlink_dat_sop => write(L, string'(" sop"));
105 when c_rlink_dat_eop => write(L, string'(" eop"));
106 when c_rlink_dat_nak => write(L, string'(" nak"));
107 when c_rlink_dat_attn => write(L, string'(" attn"));
108 when others => write(L, string'(" clobber|oob"));
109 end case;
110 end if;
111
112 if DWIDTH = 8 then
113
114 if edata then
115 write(L, string'(" edata"));
116 if data(c_cdata_edf_pref) /= c_cdata_ed_pref or
117 (not data(c_cdata_edf_eci)) /= data(c_cdata_edf_ec) then
118 write(L, string'(" FAIL: bad format"));
119 else
120 write(L, string'(" ec="));
121 write(L, data(c_cdata_edf_ec));
122 data9 := (others=>'0');
123 data9(8) := '1';
124 data9(c_cdata_edf_ec) := data(c_cdata_edf_ec);
125 case data9 is
126 when c_rlink_dat_sop => write(L, string'(" (sop)"));
127 when c_rlink_dat_eop => write(L, string'(" (eop)"));
128 when c_rlink_dat_nak => write(L, string'(" (nak)"));
129 when c_rlink_dat_attn => write(L, string'(" (attn)"));
130 when "100000" & c_cdata_ec_xon => write(L, string'(" (xon)"));
131 when "100000" & c_cdata_ec_xoff => write(L, string'(" (xoff)"));
132 when "100000" & c_cdata_ec_fill => write(L, string'(" (fill)"));
133 when "100000" & c_cdata_ec_esc => write(L, string'(" (esc)"));
134 when others =>
135 write(L, string'(" FAIL: bad ec"));
136 end case;
137 end if;
138 end if;
139
140 if data = c_cdata_escape then
141 write(L, string'(" escape"));
142 end if;
143 end if;
144
145 writeline(output, L);
146 end procedure write_val;
147
148 begin
149
150 loop
151
152 if ENA='0' then -- if disabled
153 wait until ENA='1'; -- stall process till enabled
154 end if;
155
156 wait until rising_edge(CLK); -- check at end of clock cycle
157
158 if RL_ENA = '1' then
159 if RL_BUSY = '1' then
160 nbusy := nbusy + 1;
161 else
162 write_val(oline, RL_DI, nbusy, "rx", " nbusy=", edatarx);
163 edatarx := RL_DI=c_cdata_escape;
164 nbusy := 0;
165 end if;
166 else
167 nbusy := 0;
168 end if;
169
170 if RL_VAL = '1' then
171 if RL_HOLD = '1' then
172 nhold := nhold + 1;
173 else
174 write_val(oline, RL_DO, nhold, "tx", " nhold=", edatatx);
175 edatatx := RL_DO=c_cdata_escape;
176 nhold := 0;
177 end if;
178 else
179 nhold := 0;
180 end if;
181
182 end loop;
183 end process proc_moni;
184
185end sim;
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31