22use ieee.std_logic_1164.
all;
23use ieee.numeric_std.
all;
67 proc_regs:
process (
CLK)
70 if rising_edge(CLK) then
78 end process proc_regs;
108 if r.escseen = '1' then
112 if r.rxval = '0' then
114 if r.escseen = '1' then
125 if r.rxval='1' and RXHOLD='0' then
136 end process proc_next;
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
regs_type :=( '1', '0',( others => '0'), '0', '0') regs_init
std_logic_vector( 7 downto 0) slv8