w11 - vhd 0.794
W11 CPU core and support modules
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serport_xonrx.vhd
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1-- $Id: serport_xonrx.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: serport_xonrx - syn
7-- Description: serial port: xon/xoff logic rx path
8--
9-- Dependencies: -
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: ise 13.1-14.7; viv 2014.4-2016.2; ghdl 0.29-0.33
13-- Revision History:
14-- Date Rev Version Comment
15-- 2011-10-22 417 1.0 Initial version
16------------------------------------------------------------------------------
17-- NOTE: for test bench usage a copy of all serport_* entities, with _tb
18-- !!!! appended to the name, has been created in the /tb sub folder.
19-- !!!! Ensure to update the copy when this file is changed !!
20
21library ieee;
22use ieee.std_logic_1164.all;
23use ieee.numeric_std.all;
24
25use work.slvtypes.all;
26use work.serportlib.all;
27
28entity serport_xonrx is -- serial port: xon/xoff logic rx path
29 port (
30 CLK : in slbit; -- clock
31 RESET : in slbit; -- reset
32 ENAXON : in slbit; -- enable xon/xoff handling
33 ENAESC : in slbit; -- enable xon/xoff escaping
34 UART_RXDATA : in slv8; -- uart data out
35 UART_RXVAL : in slbit; -- uart data valid
36 RXDATA : out slv8; -- user data out
37 RXVAL : out slbit; -- user data valid
38 RXHOLD : in slbit; -- user data hold
39 RXOVR : out slbit; -- user data overrun
40 TXOK : out slbit -- tx channel ok
41 );
43
44
45architecture syn of serport_xonrx is
46
47 type regs_type is record
48 txok : slbit; -- tx channel ok state
49 escseen : slbit; -- escape seen
50 rxdata : slv8; -- user rxdata
51 rxval : slbit; -- user rxval
52 rxovr : slbit; -- user rxovr
53 end record regs_type;
54
55 constant regs_init : regs_type := (
56 '1', -- txok (startup default is ok !!)
57 '0', -- escseen
58 (others=>'0'), -- rxdata
59 '0','0' -- rxval,rxovr
60 );
61
62 signal R_REGS : regs_type := regs_init; -- state registers
63 signal N_REGS : regs_type := regs_init; -- next value state regs
64
65begin
66
67 proc_regs: process (CLK)
68 begin
69
70 if rising_edge(CLK) then
71 if RESET = '1' then
73 else
74 R_REGS <= N_REGS;
75 end if;
76 end if;
77
78 end process proc_regs;
79
80 proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
81
82 variable r : regs_type := regs_init;
83 variable n : regs_type := regs_init;
84
85 begin
86
87 r := R_REGS;
88 n := R_REGS;
89
90 if ENAXON = '0' then
91 n.txok := '1';
92 end if;
93 if ENAESC = '0' then
94 n.escseen := '0';
95 end if;
96
97 n.rxovr := '0'; -- ensure single clock pulse
98
99 if UART_RXVAL = '1' then
100 if ENAXON='1' and UART_RXDATA=c_serport_xon then
101 n.txok := '1';
102 elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
103 n.txok := '0';
104 elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
105 n.escseen := '1';
106
107 else
108 if r.escseen = '1' then
109 n.escseen := '0';
110 end if;
111
112 if r.rxval = '0' then
113 n.rxval := '1';
114 if r.escseen = '1' then
115 n.rxdata := not UART_RXDATA;
116 else
117 n.rxdata := UART_RXDATA;
118 end if;
119 else
120 n.rxovr := '1';
121 end if;
122 end if;
123 end if;
124
125 if r.rxval='1' and RXHOLD='0' then
126 n.rxval := '0';
127 end if;
128
129 N_REGS <= n;
130
131 RXDATA <= r.rxdata;
132 RXVAL <= r.rxval;
133 RXOVR <= r.rxovr;
134 TXOK <= r.txok;
135
136 end process proc_next;
137
138end syn;
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
regs_type :=( '1', '0',( others => '0'), '0', '0') regs_init
in RESET slbit
out TXOK slbit
in ENAESC slbit
in ENAXON slbit
in UART_RXDATA slv8
in CLK slbit
out RXDATA slv8
out RXVAL slbit
in RXHOLD slbit
out RXOVR slbit
in UART_RXVAL slbit
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40