w11 - vhd 0.794
W11 CPU core and support modules
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serportlib.vhd
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1-- $Id: serportlib.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Package Name: serportlib
7-- Description: serial port interface components
8--
9-- Dependencies: -
10-- Tool versions: ise 8.2-14.7; viv 2014.4-2015.4; ghdl 0.18-0.33
11--
12-- Revision History:
13-- Date Rev Version Comment
14-- 2016-03-25 752 1.3.2 add serport_2clock2
15-- 2015-04-11 666 1.3.1 add serport_master
16-- 2015-02-01 641 1.3 add CLKDIV_F for autobaud
17-- 2013-01-26 476 1.2.6 renamed package to serportlib
18-- 2011-12-09 437 1.2.5 rename stat->moni port
19-- 2011-10-23 419 1.2.4 remove serport_clkdiv_ consts
20-- 2011-10-22 417 1.2.3 add serport_xon(rx|tx) defs
21-- 2011-10-14 416 1.2.2 add c_serport defs
22-- 2010-12-26 348 1.2.1 add ABCLKDIV to serport_uart_rxtx_ab
23-- 2010-04-10 276 1.2 add clock divider constant defs
24-- 2007-10-22 88 1.1 renames (in prev revs); remove std_logic_unsigned
25-- 2007-06-03 45 1.0 Initial version
26------------------------------------------------------------------------------
27-- Note: for test bench usage a copy of many serport_* entities, with -tb
28-- appended to the name, has been created in the /tb sub folder.
29-- Ensure to update the copy when this file is changed !!
30
31library ieee;
32use ieee.std_logic_1164.all;
33
34use work.slvtypes.all;
35
36package serportlib is
37
38 constant c_serport_xon : slv8 := "00010001"; -- char xon: ^Q = hex 11
39 constant c_serport_xoff : slv8 := "00010011"; -- char xoff ^S = hex 13
40 constant c_serport_xesc : slv8 := "00011011"; -- char xesc ^[ = ESC = hex 1B
41
42component serport_uart_rxtx is -- serial port uart: rx+tx combo
43 generic (
44 CDWIDTH : positive := 13); -- clk divider width
45 port (
46 CLK : in slbit; -- clock
47 RESET : in slbit; -- reset
48 CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
49 RXSD : in slbit; -- receive serial data (uart view)
50 RXDATA : out slv8; -- receiver data out
51 RXVAL : out slbit; -- receiver data valid
52 RXERR : out slbit; -- receiver data error (frame error)
53 RXACT : out slbit; -- receiver active
54 TXSD : out slbit; -- transmit serial data (uart view)
55 TXDATA : in slv8; -- transmit data in
56 TXENA : in slbit; -- transmit data enable
57 TXBUSY : out slbit -- transmit busy
58 );
59end component;
60
61component serport_uart_rx is -- serial port uart: receive part
62 generic (
63 CDWIDTH : positive := 13); -- clk divider width
64 port (
65 CLK : in slbit; -- clock
66 RESET : in slbit; -- reset
67 CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
68 RXSD : in slbit; -- receive serial data (uart view)
69 RXDATA : out slv8; -- receiver data out
70 RXVAL : out slbit; -- receiver data valid
71 RXERR : out slbit; -- receiver data error (frame error)
72 RXACT : out slbit -- receiver active
73 );
74end component;
75
76component serport_uart_tx is -- serial port uart: transmit part
77 generic (
78 CDWIDTH : positive := 13); -- clk divider width
79 port (
80 CLK : in slbit; -- clock
81 RESET : in slbit; -- reset
82 CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
83 TXSD : out slbit; -- transmit serial data (uart view)
84 TXDATA : in slv8; -- transmit data in
85 TXENA : in slbit; -- transmit data enable
86 TXBUSY : out slbit -- transmit busy
87 );
88end component;
89
90component serport_uart_rxtx_ab is -- serial port uart: rx+tx+autobaud
91 generic (
92 CDWIDTH : positive := 13; -- clk divider width
93 CDINIT: natural := 15); -- clk divider initial/reset setting
94 port (
95 CLK : in slbit; -- clock
96 CE_MSEC : in slbit; -- 1 msec clock enable
97 RESET : in slbit; -- reset
98 RXSD : in slbit; -- receive serial data (uart view)
99 RXDATA : out slv8; -- receiver data out
100 RXVAL : out slbit; -- receiver data valid
101 RXERR : out slbit; -- receiver data error (frame error)
102 RXACT : out slbit; -- receiver active
103 TXSD : out slbit; -- transmit serial data (uart view)
104 TXDATA : in slv8; -- transmit data in
105 TXENA : in slbit; -- transmit data enable
106 TXBUSY : out slbit; -- transmit busy
107 ABACT : out slbit; -- autobaud active; if 1 clkdiv invalid
108 ABDONE : out slbit; -- autobaud resync done
109 ABCLKDIV : out slv(CDWIDTH-1 downto 0); -- autobaud clock divider setting
110 ABCLKDIV_F : out slv3 -- autobaud clock divider fraction
111 );
112end component;
113
114component serport_uart_autobaud is -- serial port uart: autobauder
115 generic (
116 CDWIDTH : positive := 13; -- clk divider width
117 CDINIT: natural := 15); -- clk divider initial/reset setting
118 port (
119 CLK : in slbit; -- clock
120 CE_MSEC : in slbit; -- 1 msec clock enable
121 RESET : in slbit; -- reset
122 RXSD : in slbit; -- receive serial data (uart view)
123 CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
124 CLKDIV_F: out slv3; -- clock divider fractional part
125 ACT : out slbit; -- active; if 1 clkdiv is invalid
126 DONE : out slbit -- resync done
127 );
128end component;
129
130component serport_xonrx is -- serial port: xon/xoff logic rx path
131 port (
132 CLK : in slbit; -- clock
133 RESET : in slbit; -- reset
134 ENAXON : in slbit; -- enable xon/xoff handling
135 ENAESC : in slbit; -- enable xon/xoff escaping
136 UART_RXDATA : in slv8; -- uart data out
137 UART_RXVAL : in slbit; -- uart data valid
138 RXDATA : out slv8; -- user data out
139 RXVAL : out slbit; -- user data valid
140 RXHOLD : in slbit; -- user data hold
141 RXOVR : out slbit; -- user data overrun
142 TXOK : out slbit -- tx channel ok
143 );
144end component;
145
146component serport_xontx is -- serial port: xon/xoff logic tx path
147 port (
148 CLK : in slbit; -- clock
149 RESET : in slbit; -- reset
150 ENAXON : in slbit; -- enable xon/xoff handling
151 ENAESC : in slbit; -- enable xon/xoff escaping
152 UART_TXDATA : out slv8; -- uart data in
153 UART_TXENA : out slbit; -- uart data enable
154 UART_TXBUSY : in slbit; -- uart data busy
155 TXDATA : in slv8; -- user data in
156 TXENA : in slbit; -- user data enable
157 TXBUSY : out slbit; -- user data busy
158 RXOK : in slbit; -- rx channel ok
159 TXOK : in slbit -- tx channel ok
160 );
161end component;
162
163type serport_moni_type is record -- serport monitor port
164 rxerr : slbit; -- receiver data error (frame error)
165 rxovr : slbit; -- receiver data overrun
166 rxact : slbit; -- receiver active
167 txact : slbit; -- transceiver active
168 abact : slbit; -- autobauder active;if 1 clkdiv invalid
169 abdone : slbit; -- autobauder resync done
170 abclkdiv : slv16; -- autobauder clock divider
171 abclkdiv_f : slv3; -- autobauder clock divider fraction
172 rxok : slbit; -- rx channel ok
173 txok : slbit; -- tx channel ok
174end record serport_moni_type;
175
177 '0','0', -- rxerr,rxovr
178 '0','0', -- rxact,txact
179 '0','0', -- abact,abdone
180 (others=>'0'), -- abclkdiv
181 (others=>'0'), -- abclkdiv_f
182 '0','0' -- rxok,txok
183);
184
185component serport_1clock is -- serial port module, 1 clock domain
186 generic (
187 CDWIDTH : positive := 13; -- clk divider width
188 CDINIT : natural := 15; -- clk divider initial/reset setting
189 RXFAWIDTH : natural := 5; -- rx fifo address width
190 TXFAWIDTH : natural := 5); -- tx fifo address width
191 port (
192 CLK : in slbit; -- clock
193 CE_MSEC : in slbit; -- 1 msec clock enable
194 RESET : in slbit; -- reset
195 ENAXON : in slbit; -- enable xon/xoff handling
196 ENAESC : in slbit; -- enable xon/xoff escaping
197 RXDATA : out slv8; -- receiver data out
198 RXVAL : out slbit; -- receiver data valid
199 RXHOLD : in slbit; -- receiver data hold
200 TXDATA : in slv8; -- transmit data in
201 TXENA : in slbit; -- transmit data enable
202 TXBUSY : out slbit; -- transmit busy
203 MONI : out serport_moni_type; -- serport monitor port
204 RXSD : in slbit; -- receive serial data (uart view)
205 TXSD : out slbit; -- transmit serial data (uart view)
206 RXRTS_N : out slbit; -- receive rts (uart view, act.low)
207 TXCTS_N : in slbit -- transmit cts (uart view, act.low)
208 );
209end component;
210
211component serport_2clock is -- serial port module, 2 clock domain
212 generic (
213 CDWIDTH : positive := 13; -- clk divider width
214 CDINIT : natural := 15; -- clk divider initial/reset setting
215 RXFAWIDTH : natural := 5; -- rx fifo address width
216 TXFAWIDTH : natural := 5); -- tx fifo address width
217 port (
218 CLKU : in slbit; -- clock (backend:user)
219 RESET : in slbit; -- reset
220 CLKS : in slbit; -- clock (frontend:serial)
221 CES_MSEC : in slbit; -- S|1 msec clock enable
222 ENAXON : in slbit; -- U|enable xon/xoff handling
223 ENAESC : in slbit; -- U|enable xon/xoff escaping
224 RXDATA : out slv8; -- U|receiver data out
225 RXVAL : out slbit; -- U|receiver data valid
226 RXHOLD : in slbit; -- U|receiver data hold
227 TXDATA : in slv8; -- U|transmit data in
228 TXENA : in slbit; -- U|transmit data enable
229 TXBUSY : out slbit; -- U|transmit busy
230 MONI : out serport_moni_type; -- U|serport monitor port
231 RXSD : in slbit; -- S|receive serial data (uart view)
232 TXSD : out slbit; -- S|transmit serial data (uart view)
233 RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
234 TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
235 );
236end component;
237
238component serport_2clock2 is -- serial port module, 2 clock dom. (v2)
239 generic (
240 CDWIDTH : positive := 13; -- clk divider width
241 CDINIT : natural := 15; -- clk divider initial/reset setting
242 RXFAWIDTH : natural := 5; -- rx fifo address width
243 TXFAWIDTH : natural := 5); -- tx fifo address width
244 port (
245 CLKU : in slbit; -- U|clock (backend:user)
246 RESET : in slbit; -- U|reset
247 CLKS : in slbit; -- S|clock (frontend:serial)
248 CES_MSEC : in slbit; -- S|1 msec clock enable
249 ENAXON : in slbit; -- U|enable xon/xoff handling
250 ENAESC : in slbit; -- U|enable xon/xoff escaping
251 RXDATA : out slv8; -- U|receiver data out
252 RXVAL : out slbit; -- U|receiver data valid
253 RXHOLD : in slbit; -- U|receiver data hold
254 TXDATA : in slv8; -- U|transmit data in
255 TXENA : in slbit; -- U|transmit data enable
256 TXBUSY : out slbit; -- U|transmit busy
257 MONI : out serport_moni_type; -- U|serport monitor port
258 RXSD : in slbit; -- S|receive serial data (uart view)
259 TXSD : out slbit; -- S|transmit serial data (uart view)
260 RXRTS_N : out slbit; -- S|receive rts (uart view, act.low)
261 TXCTS_N : in slbit -- S|transmit cts (uart view, act.low)
262 );
263end component;
264
265component serport_master is -- serial port module, master side
266 generic (
267 CDWIDTH : positive := 13); -- clk divider width
268 port (
269 CLK : in slbit; -- clock
270 RESET : in slbit; -- reset
271 CLKDIV : in slv(CDWIDTH-1 downto 0); -- clock divider setting
272 ENAXON : in slbit := '0'; -- enable xon/xoff handling
273 ENAESC : in slbit := '0'; -- enable xon/xoff escaping
274 RXDATA : out slv8; -- receiver data out
275 RXVAL : out slbit; -- receiver data valid
276 RXERR : out slbit; -- receiver data error (frame error)
277 RXOK : in slbit := '1'; -- rx channel ok
278 TXDATA : in slv8; -- transmit data in
279 TXENA : in slbit; -- transmit data enable
280 TXBUSY : out slbit; -- transmit busy
281 RXSD : in slbit; -- receive serial data (uart view)
282 TXSD : out slbit; -- transmit serial data (uart view)
283 RXRTS_N : out slbit; -- receive rts (uart view, act.low)
284 TXCTS_N : in slbit :='0' -- transmit cts (uart view, act.low)
285 );
286end component;
287
288end package serportlib;
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
in CE_MSEC slbit
out TXBUSY slbit
TXFAWIDTH natural := 5
CDWIDTH positive := 13
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
out TXBUSY slbit
in CES_MSEC slbit
out CLKDIV slv( CDWIDTH- 1 downto 0)
CDWIDTH positive := 13
in CLKDIV slv( CDWIDTH- 1 downto 0)
out ABCLKDIV slv( CDWIDTH- 1 downto 0)
CDWIDTH positive := 13
in CLKDIV slv( CDWIDTH- 1 downto 0)
CDWIDTH positive := 13
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RESET slbit
out TXOK slbit
in ENAESC slbit
in ENAXON slbit
in UART_RXDATA slv8
in CLK slbit
out RXDATA slv8
out RXVAL slbit
in RXHOLD slbit
out RXOVR slbit
in UART_RXVAL slbit
in RESET slbit
in TXENA slbit
out UART_TXENA slbit
in TXOK slbit
in ENAESC slbit
in ENAXON slbit
in TXDATA slv8
in CLK slbit
out UART_TXDATA slv8
in RXOK slbit
out TXBUSY slbit
in UART_TXBUSY slbit
slv8 := "00011011" c_serport_xesc
Definition: serportlib.vhd:40
slv8 := "00010011" c_serport_xoff
Definition: serportlib.vhd:39
serport_moni_type :=( '0', '0', '0', '0', '0', '0',( others => '0'),( others => '0'), '0', '0') serport_moni_init
Definition: serportlib.vhd:176
slv8 := "00010001" c_serport_xon
Definition: serportlib.vhd:38
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31