w11 - vhd 0.794
W11 CPU core and support modules
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sys_tst_snhumanio_n4.vhd
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1-- $Id: sys_tst_snhumanio_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_snhumanio_n4 - syn
7-- Description: snhumanio tester design for nexys4
8--
9-- Dependencies: vlib/genlib/clkdivce
10-- bplib/bpgen/sn_humanio
11-- tst_snhumanio
12--
13-- Test bench: -
14--
15-- Target Devices: generic
16-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
17--
18-- Synthesized:
19-- Date Rev viv Target flop lutl lutm bram slic
20-- 2019-02-02 1108 2018.3 xc7a100t-1 154 187 0 0 69
21-- 2019-02-02 1108 2017.2 xc7a100t-1 154 185 0 0 68
22-- 2015-01-31 640 2014.4 xc7a100t-1 154 133 0 0 56
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2015-02-06 643 1.1 factor out memory
27-- 2015-02-01 641 1.0.1 separate I_BTNRST_N
28-- 2015-01-31 640 1.0 Initial version
29------------------------------------------------------------------------------
30-- Usage of Nexys 4 Switches, Buttons, LEDs:
31--
32
33library ieee;
34use ieee.std_logic_1164.all;
35
36use work.slvtypes.all;
37use work.genlib.all;
38use work.bpgenlib.all;
39use work.sys_conf.all;
40
41-- ----------------------------------------------------------------------------
42
43entity sys_tst_snhumanio_n4 is -- top level
44 -- implements nexys4_aif
45 port (
46 I_CLK100 : in slbit; -- 100 MHz clock
47 I_RXD : in slbit; -- receive data (board view)
48 O_TXD : out slbit; -- transmit data (board view)
49 O_RTS_N : out slbit; -- rx rts (board view; act.low)
50 I_CTS_N : in slbit; -- tx cts (board view; act.low)
51 I_SWI : in slv16; -- n4 switches
52 I_BTN : in slv5; -- n4 buttons
53 I_BTNRST_N : in slbit; -- n4 reset button
54 O_LED : out slv16; -- n4 leds
55 O_RGBLED0 : out slv3; -- n4 rgb-led 0
56 O_RGBLED1 : out slv3; -- n4 rgb-led 1
57 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
58 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
59 );
61
62architecture syn of sys_tst_snhumanio_n4 is
63
64 signal CLK : slbit := '0';
65
66 signal SWI : slv8 := (others=>'0');
67 signal BTN : slv5 := (others=>'0');
68 signal LED : slv8 := (others=>'0');
69 signal DSP_DAT : slv16 := (others=>'0');
70 signal DSP_DP : slv4 := (others=>'0');
71
72 signal RESET : slbit := '0';
73 signal CE_MSEC : slbit := '0';
74
75begin
76
77 RESET <= '0'; -- so far not used
78
79 CLK <= I_CLK100;
80
81 CLKDIV : clkdivce
82 generic map (
83 CDUWIDTH => 7,
84 USECDIV => 100,
85 MSECDIV => 1000)
86 port map (
87 CLK => CLK,
88 CE_USEC => open,
90 );
91
92 HIO : sn_humanio
93 generic map (
94 BWIDTH => 5,
95 DEBOUNCE => sys_conf_hio_debounce)
96 port map (
97 CLK => CLK,
98 RESET => RESET,
100 SWI => SWI,
101 BTN => BTN,
102 LED => LED,
103 DSP_DAT => DSP_DAT,
104 DSP_DP => DSP_DP,
105 I_SWI => I_SWI(7 downto 0),
106 I_BTN => I_BTN,
107 O_LED => O_LED(7 downto 0),
108 O_ANO_N => O_ANO_N(3 downto 0),
110 );
111
112 HIOTEST : entity work.tst_snhumanio
113 generic map (
114 BWIDTH => 5)
115 port map (
116 CLK => CLK,
117 RESET => RESET,
118 CE_MSEC => CE_MSEC,
119 SWI => SWI,
120 BTN => BTN,
121 LED => LED,
122 DSP_DAT => DSP_DAT,
123 DSP_DP => DSP_DP
124 );
125
126 O_TXD <= I_RXD;
127 O_RTS_N <= I_CTS_N;
128
129 O_LED(15 downto 8) <= not I_SWI(15 downto 8);
130 O_ANO_N(7 downto 4) <= (others=>'1');
131
132 O_RGBLED0 <= (others=>'0');
133 O_RGBLED1 <= (others=>not I_BTNRST_N);
134
135end syn;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
slv8 :=( others => '0') SWI
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
in RESET slbit
out DSP_DP slv4
in CLK slbit
in BTN slv( BWIDTH- 1 downto 0)
BWIDTH positive := 4
out DSP_DAT slv16
out LED slv8
in CE_MSEC slbit