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W11 CPU core and support modules
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sysmonx_rbus_arty.vhd
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1-- $Id: sysmonx_rbus_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sysmonx_rbus_arty - syn
7-- Description: 7series XADC interface to rbus (arty pwrmon version)
8--
9-- Dependencies: sysmon_rbus_core
10--
11-- Test bench: -
12--
13-- Target Devices: 7series
14-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
15--
16-- Revision History:
17-- Date Rev Version Comment
18-- 2016-03-12 741 1.0 Initial version
19-- 2016-03-06 738 0.1 First draft
20------------------------------------------------------------------------------
21--
22-- rbus registers: see sysmon_rbus_core and XADC user guide
23--
24-- XADC usage:
25-- - build-in sensors: temp, Vccint, Vccaux, Vccbram
26-- - arty power monitoring:
27-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line)
28-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack)
29-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line)
30-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core)
31--
32
33library ieee;
34use ieee.std_logic_1164.all;
35use ieee.numeric_std.all;
36
37library unisim;
38use unisim.vcomponents.ALL;
39
40use work.slvtypes.all;
41use work.rblib.all;
42use work.sysmonrbuslib.all;
43
44-- ----------------------------------------------------------------------------
45
46entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty)
47 generic (
48 INIT_OT_LIMIT : real := 125.0; -- INIT_53
49 INIT_OT_RESET : real := 70.0; -- INIT_57
50 INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
51 INIT_TEMP_LOW : real := 60.0; -- INIT_54
52 INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
53 INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
54 INIT_VCCAUX_UP : real := 1.89; -- INIT_52
55 INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
56 INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
57 INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
58 CLK_MHZ : integer := 250; -- clock frequency in MHz
59 RB_ADDR : slv16 := x"fb00");
60 port (
61 CLK : in slbit; -- clock
62 RESET : in slbit := '0'; -- reset
63 RB_MREQ : in rb_mreq_type; -- rbus: request
64 RB_SRES : out rb_sres_type; -- rbus: response
65 ALM : out slv8; -- xadc: alarms
66 OT : out slbit; -- xadc: over temp
67 TEMP : out slv12; -- xadc: die temp
68 VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
69 VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
70 );
72
73architecture syn of sysmonx_rbus_arty is
74
75 constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux
76 constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux
77 constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux
78 constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux
79
80 constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
81 constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
82
83 constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon)
84 vpwrmap_1 => '1',
85 vpwrmap_2 => '1',
86 vpwrmap_3 => '1',
87 others => '0');
88
89 signal VAUXN : slv16 := (others=>'0');
90 signal VAUXP : slv16 := (others=>'0');
91
92 signal SM_DEN : slbit := '0';
93 signal SM_DWE : slbit := '0';
94 signal SM_DADDR : slv7 := (others=>'0');
95 signal SM_DI : slv16 := (others=>'0');
96 signal SM_DO : slv16 := (others=>'0');
97 signal SM_DRDY : slbit := '0';
98 signal SM_EOS : slbit := '0';
99 signal SM_EOC : slbit := '0';
100 signal SM_RESET : slbit := '0';
101 signal SM_CHAN : slv5 := (others=>'0');
102 signal SM_ALM : slv8 := (others=>'0');
103 signal SM_OT : slbit := '0';
104 signal SM_JTAGLOCKED : slbit := '0';
105 signal SM_JTAGMODIFIED : slbit := '0';
106 signal SM_JTAGBUSY : slbit := '0';
107
108begin
109
110 SM : XADC
111 generic map (
112 INIT_40 => xadc_init_40_default, -- conf #0
113 INIT_41 => xadc_init_41_default, -- conf #1
114 INIT_42 => init_42,
115 INIT_43 => x"0000", -- test #0 - don't use, stay 0
116 INIT_44 => x"0000", -- test #1 - "
117 INIT_45 => x"0000", -- test #2 - "
118 INIT_46 => x"0000", -- test #3 - "
119 INIT_47 => x"0000", -- test #4 - "
120 INIT_48 => xadc_init_48_default, -- seq #0: sel 0
121 INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon)
122 INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
123 INIT_4B => x"0000", -- seq #3: avr 1: "
124 INIT_4C => x"0000", -- seq #4: mode 0: unipolar
125 INIT_4D => x"0000", -- seq #5: mode 1: "
126 INIT_4E => x"0000", -- seq #6: time 0: fast
127 INIT_4F => x"0000", -- seq #7: time 1: "
128 INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
129 INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
130 INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
131 INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
132 INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
133 INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
134 INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
135 INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
136 INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
137 INIT_59 => x"0000", -- alm #09: ccpint up (4)
138 INIT_5A => x"0000", -- alm #10: ccpaux up (5)
139 INIT_5B => x"0000", -- alm #11: ccdram up (6)
140 INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
141 INIT_5D => x"0000", -- alm #13: ccpint low (4)
142 INIT_5E => x"0000", -- alm #14: ccpaux low (5)
143 INIT_5F => x"0000", -- alm #15: ccdram low (6)
144-- IS_CONVSTCLK_INVERTED => '0',
145-- IS_DCLK_INVERTED => '0',
146 SIM_DEVICE => "7SERIES",
147 SIM_MONITOR_FILE => "sysmon_stim")
148 port map (
149 DCLK => CLK,
150 DEN => SM_DEN,
151 DWE => SM_DWE,
152 DADDR => SM_DADDR,
153 DI => SM_DI,
154 DO => SM_DO,
155 DRDY => SM_DRDY,
156 EOC => SM_EOC, -- connected for tb usage
157 EOS => SM_EOS,
158 BUSY => open,
159 RESET => SM_RESET,
160 CHANNEL => SM_CHAN, -- connected for tb usage
161 MUXADDR => open,
162 ALM => SM_ALM,
163 OT => SM_OT,
164 CONVST => '0',
165 CONVSTCLK => '0',
166 JTAGBUSY => SM_JTAGBUSY,
167 JTAGLOCKED => SM_JTAGLOCKED,
168 JTAGMODIFIED => SM_JTAGMODIFIED,
169 VAUXN => VAUXN,
170 VAUXP => VAUXP,
171 VN => '0',
172 VP => '0'
173 );
174
175 VAUXN <= (vpwrmap_0 => VPWRN(0),
176 vpwrmap_1 => VPWRN(1),
177 vpwrmap_2 => VPWRN(2),
178 vpwrmap_3 => VPWRN(3),
179 others=>'0');
180 VAUXP <= (vpwrmap_0 => VPWRP(0),
181 vpwrmap_1 => VPWRP(1),
182 vpwrmap_2 => VPWRP(2),
183 vpwrmap_3 => VPWRP(3),
184 others=>'0');
185
186 SMRB : sysmon_rbus_core
187 generic map (
188 DAWIDTH => 7,
189 ALWIDTH => 8,
190 TEWIDTH => 12,
191 IBASE => x"78",
192 RB_ADDR => RB_ADDR)
193 port map (
194 CLK => CLK,
195 RESET => RESET,
196 RB_MREQ => RB_MREQ,
197 RB_SRES => RB_SRES,
198 SM_DEN => SM_DEN,
199 SM_DWE => SM_DWE,
201 SM_DI => SM_DI,
202 SM_DO => SM_DO,
203 SM_DRDY => SM_DRDY,
204 SM_EOS => SM_EOS,
206 SM_ALM => SM_ALM,
207 SM_OT => SM_OT,
211 TEMP => TEMP
212 );
213
214 ALM <= SM_ALM;
215 OT <= SM_OT;
216
217end syn;
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 6 downto 0) slv7
Definition: slvtypes.vhd:39
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31
TEWIDTH positive := 12
out SM_DADDR slv( DAWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
in SM_JTAGMODIFIED slbit
DAWIDTH positive := 7
in SM_ALM slv( ALWIDTH- 1 downto 0)
IBASE slv8 := x"78"
out RB_SRES rb_sres_type
out TEMP slv( TEWIDTH- 1 downto 0)
ALWIDTH positive := 8
in RESET slbit := '0'
slv7 :=( others => '0') SM_DADDR
slv16 :=( others => '0') SM_DO
bv16 :=( vpwrmap_0=> '1', vpwrmap_1=> '1', vpwrmap_2=> '1', vpwrmap_3=> '1', others => '0') init_49
integer :=( CLK_MHZ+ 25)/ 26 conf2_cd
slv16 :=( others => '0') VAUXN
slv5 :=( others => '0') SM_CHAN
bv16 := to_bitvector( slv( to_unsigned( 256* conf2_cd, 16) ) ) init_42
slv16 :=( others => '0') VAUXP
slv8 :=( others => '0') SM_ALM
slv16 :=( others => '0') SM_DI
in VPWRP slv4 :=( others => '0')
INIT_VCCAUX_UP real := 1.89
INIT_TEMP_LOW real := 60.0
INIT_OT_RESET real := 70.0
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
INIT_TEMP_UP real := 85.0
INIT_VCCINT_LOW real := 0.92
out RB_SRES rb_sres_type
INIT_VCCBRAM_LOW real := 0.92
in VPWRN slv4 :=( others => '0')
in RESET slbit := '0'
INIT_VCCAUX_LOW real := 1.71
INIT_OT_LIMIT real := 125.0
INIT_VCCINT_UP real := 0.98
INIT_VCCBRAM_UP real := 0.98