34use ieee.std_logic_1164.
all;
35use ieee.numeric_std.
all;
38use unisim.vcomponents.
ALL;
112 INIT_40 => xadc_init_40_default,
113 INIT_41 => xadc_init_41_default,
120 INIT_48 => xadc_init_48_default,
122 INIT_4A => xadc_init_4a_default,
131 INIT_53 => xadc_init_53_default,
135 INIT_57 => xadc_init_57_default,
146 SIM_DEVICE =>
"7SERIES",
147 SIM_MONITOR_FILE =>
"sysmon_stim")
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
out SM_DADDR slv( DAWIDTH- 1 downto 0)
in SM_ALM slv( ALWIDTH- 1 downto 0)
out TEMP slv( TEWIDTH- 1 downto 0)
slv7 :=( others => '0') SM_DADDR
slv16 :=( others => '0') SM_DO
bv16 :=( vpwrmap_0=> '1', vpwrmap_1=> '1', vpwrmap_2=> '1', vpwrmap_3=> '1', others => '0') init_49
integer :=( CLK_MHZ+ 25)/ 26 conf2_cd
slv16 :=( others => '0') VAUXN
slv5 :=( others => '0') SM_CHAN
bv16 := to_bitvector( slv( to_unsigned( 256* conf2_cd, 16) ) ) init_42
slbit := '0' SM_JTAGMODIFIED
slv16 :=( others => '0') VAUXP
slbit := '0' SM_JTAGLOCKED
slv8 :=( others => '0') SM_ALM
slv16 :=( others => '0') SM_DI
in VPWRP slv4 :=( others => '0')
INIT_VCCAUX_UP real := 1.89
INIT_TEMP_LOW real := 60.0
INIT_OT_RESET real := 70.0
INIT_TEMP_UP real := 85.0
INIT_VCCINT_LOW real := 0.92
INIT_VCCBRAM_LOW real := 0.92
in VPWRN slv4 :=( others => '0')
INIT_VCCAUX_LOW real := 1.71
INIT_OT_LIMIT real := 125.0
INIT_VCCINT_UP real := 0.98
INIT_VCCBRAM_UP real := 0.98