34use ieee.std_logic_1164.
all;
35use ieee.numeric_std.
all;
36use ieee.std_logic_textio.
all;
156 variable oline : line;
160 wait until rising_edge(CLKCOM);
164 writeline(output, oline);
169 end process proc_moni;
177 proc_simbus:
process (SB_VAL)
179 if SB_VAL'event and to_x01(SB_VAL)='1' then
184 end process proc_simbus;
in CLKDIV slv( CDWIDTH- 1 downto 0)
VCO_MULTIPLY positive := 1
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
Delay_length := 10 ns clock_period
slv16 :=( others => '0') O_LED
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slv5 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv4 :=( others => '0') O_ANO_N
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TXDATA
slv16 :=( others => '0') I_SWI