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W11 CPU core and support modules
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tb_basys3.vhd
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1-- $Id: tb_basys3.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_basys3 - sim
7-- Description: Test bench for basys3 (base)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_basys3_core
14-- serport/tb/serport_master_tb
15-- basys3_aif [UUT]
16--
17-- To test: generic, any basys3_aif target
18--
19-- Target Devices: generic
20-- Tool versions: viv 2014.4-2018.2; ghdl 0.31-0.34
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2018-11-03 1064 1.1.5 use sfs_gsim_core
25-- 2016-09-02 805 1.1.4 tbcore_rlink without CLK_STOP now
26-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict
27-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink
28-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb
29-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx
30-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4)
31------------------------------------------------------------------------------
32
33library ieee;
34use ieee.std_logic_1164.all;
35use ieee.numeric_std.all;
36use ieee.std_logic_textio.all;
37use std.textio.all;
38
39use work.slvtypes.all;
40use work.rlinklib.all;
41use work.xlib.all;
42use work.basys3lib.all;
43use work.simlib.all;
44use work.simbus.all;
45use work.sys_conf.all;
46
47entity tb_basys3 is
48end tb_basys3;
49
50architecture sim of tb_basys3 is
51
52 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
53 signal CLKCOM : slbit := '0'; -- communication clock
54
55 signal CLKCOM_CYCLE : integer := 0;
56
57 signal RESET : slbit := '0';
58 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
59 signal RXDATA : slv8 := (others=>'0');
60 signal RXVAL : slbit := '0';
61 signal RXERR : slbit := '0';
62 signal RXACT : slbit := '0';
63 signal TXDATA : slv8 := (others=>'0');
64 signal TXENA : slbit := '0';
65 signal TXBUSY : slbit := '0';
66
67 signal I_RXD : slbit := '1';
68 signal O_TXD : slbit := '1';
69 signal I_SWI : slv16 := (others=>'0');
70 signal I_BTN : slv5 := (others=>'0');
71 signal O_LED : slv16 := (others=>'0');
72 signal O_ANO_N : slv4 := (others=>'0');
73 signal O_SEG_N : slv8 := (others=>'0');
74
75 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
76
77 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
78
79 constant clock_period : Delay_length := 10 ns;
80 constant clock_offset : Delay_length := 200 ns;
81
82begin
83
84 CLKGEN : simclk
85 generic map (
88 port map (
89 CLK => CLKOSC
90 );
91
92 CLKGEN_COM : sfs_gsim_core
93 generic map (
94 VCO_DIVIDE => sys_conf_clkser_vcodivide,
95 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
96 OUT_DIVIDE => sys_conf_clkser_outdivide)
97 port map (
98 CLKIN => CLKOSC,
99 CLKFX => CLKCOM,
100 LOCKED => open
101 );
102
103 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
104
105 TBCORE : entity work.tbcore_rlink
106 port map (
107 CLK => CLKCOM,
108 RX_DATA => TXDATA,
109 RX_VAL => TXENA,
110 RX_HOLD => TXBUSY,
111 TX_DATA => RXDATA,
112 TX_ENA => RXVAL
113 );
114
115 B3CORE : entity work.tb_basys3_core
116 port map (
117 I_SWI => I_SWI,
118 I_BTN => I_BTN
119 );
120
121 UUT : basys3_aif
122 port map (
123 I_CLK100 => CLKOSC,
124 I_RXD => I_RXD,
125 O_TXD => O_TXD,
126 I_SWI => I_SWI,
127 I_BTN => I_BTN,
128 O_LED => O_LED,
129 O_ANO_N => O_ANO_N,
130 O_SEG_N => O_SEG_N
131 );
132
133 SERMSTR : entity work.serport_master_tb
134 generic map (
135 CDWIDTH => CLKDIV'length)
136 port map (
137 CLK => CLKCOM,
138 RESET => RESET,
139 CLKDIV => CLKDIV,
141 ENAESC => '0',
142 RXDATA => RXDATA,
143 RXVAL => RXVAL,
144 RXERR => RXERR,
145 RXOK => '1',
146 TXDATA => TXDATA,
147 TXENA => TXENA,
148 TXBUSY => TXBUSY,
149 RXSD => O_TXD,
150 TXSD => I_RXD,
151 RXRTS_N => open,
152 TXCTS_N => '0'
153 );
154
155 proc_moni: process
156 variable oline : line;
157 begin
158
159 loop
160 wait until rising_edge(CLKCOM);
161
162 if RXERR = '1' then
163 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
164 writeline(output, oline);
165 end if;
166
167 end loop;
168
169 end process proc_moni;
170
171 --
172 -- Notes on portsel and XON control:
173 -- - most basys3 designs will use hardwired XON=1
174 -- - but some (especially basis tests) might not use flow control
175 -- - that's why XON flow control must be optional and configurable !
176 --
177 proc_simbus: process (SB_VAL)
178 begin
179 if SB_VAL'event and to_x01(SB_VAL)='1' then
180 if SB_ADDR = sbaddr_portsel then
181 R_PORTSEL_XON <= to_x01(SB_DATA(1));
182 end if;
183 end if;
184 end process proc_simbus;
185
186end sim;
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' RXERR
Definition: tb_basys3.vhd:61
slbit := '0' RESET
Definition: tb_basys3.vhd:57
slv8 :=( others => '0') O_SEG_N
Definition: tb_basys3.vhd:73
integer := 0 CLKCOM_CYCLE
Definition: tb_basys3.vhd:55
Delay_length := 10 ns clock_period
Definition: tb_basys3.vhd:79
slv2 := "00" CLKDIV
Definition: tb_basys3.vhd:58
slv16 :=( others => '0') O_LED
Definition: tb_basys3.vhd:71
slbit := '0' TXENA
Definition: tb_basys3.vhd:64
slv8 :=( others => '0') RXDATA
Definition: tb_basys3.vhd:59
Delay_length := 200 ns clock_offset
Definition: tb_basys3.vhd:80
slbit := '0' RXACT
Definition: tb_basys3.vhd:62
slv5 :=( others => '0') I_BTN
Definition: tb_basys3.vhd:70
slbit := '0' RXVAL
Definition: tb_basys3.vhd:60
slbit := '1' O_TXD
Definition: tb_basys3.vhd:68
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
Definition: tb_basys3.vhd:77
slbit := '0' CLKOSC
Definition: tb_basys3.vhd:52
slbit := '0' CLKCOM
Definition: tb_basys3.vhd:53
slbit := '0' TXBUSY
Definition: tb_basys3.vhd:65
slv4 :=( others => '0') O_ANO_N
Definition: tb_basys3.vhd:72
slbit := '0' R_PORTSEL_XON
Definition: tb_basys3.vhd:75
slv8 :=( others => '0') TXDATA
Definition: tb_basys3.vhd:63
slv16 :=( others => '0') I_SWI
Definition: tb_basys3.vhd:69
slbit := '1' I_RXD
Definition: tb_basys3.vhd:67
out I_SWI slv16
Definition: xlib.vhd:35