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W11 CPU core and support modules
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tb_nexys4.vhd
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1-- $Id: tb_nexys4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys4 - sim
7-- Description: Test bench for nexys4 (base)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_nexys4_core
14-- serport/tb/serport_master_tb
15-- nexys4_aif [UUT]
16--
17-- To test: generic, any nexys4_aif target
18--
19-- Target Devices: generic
20-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2018-11-03 1064 1.3.5 use sfs_gsim_core
25-- 2016-09-02 805 1.3.4 tbcore_rlink without CLK_STOP now
26-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
27-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
28-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
29-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
30-- 2015-02-06 643 1.2 factor out memory
31-- 2015-02-01 641 1.1 separate I_BTNRST_N
32-- 2013-09-28 535 1.0.1 use proper clock manager
33-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
34------------------------------------------------------------------------------
35
36library ieee;
37use ieee.std_logic_1164.all;
38use ieee.numeric_std.all;
39use ieee.std_logic_textio.all;
40use std.textio.all;
41
42use work.slvtypes.all;
43use work.rlinklib.all;
44use work.xlib.all;
45use work.nexys4lib.all;
46use work.simlib.all;
47use work.simbus.all;
48use work.sys_conf.all;
49
50entity tb_nexys4 is
51end tb_nexys4;
52
53architecture sim of tb_nexys4 is
54
55 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
56 signal CLKCOM : slbit := '0'; -- communication clock
57
58 signal CLKCOM_CYCLE : integer := 0;
59
60 signal RESET : slbit := '0';
61 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
62 signal RXDATA : slv8 := (others=>'0');
63 signal RXVAL : slbit := '0';
64 signal RXERR : slbit := '0';
65 signal RXACT : slbit := '0';
66 signal TXDATA : slv8 := (others=>'0');
67 signal TXENA : slbit := '0';
68 signal TXBUSY : slbit := '0';
69
70 signal I_RXD : slbit := '1';
71 signal O_TXD : slbit := '1';
72 signal O_RTS_N : slbit := '0';
73 signal I_CTS_N : slbit := '0';
74 signal I_SWI : slv16 := (others=>'0');
75 signal I_BTN : slv5 := (others=>'0');
76 signal I_BTNRST_N : slbit := '1';
77 signal O_LED : slv16 := (others=>'0');
78 signal O_RGBLED0 : slv3 := (others=>'0');
79 signal O_RGBLED1 : slv3 := (others=>'0');
80 signal O_ANO_N : slv8 := (others=>'0');
81 signal O_SEG_N : slv8 := (others=>'0');
82
83 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
84
85 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
86
87 constant clock_period : Delay_length := 10 ns;
88 constant clock_offset : Delay_length := 200 ns;
89
90begin
91
92 CLKGEN : simclk
93 generic map (
96 port map (
97 CLK => CLKOSC
98 );
99
100 CLKGEN_COM : sfs_gsim_core
101 generic map (
102 VCO_DIVIDE => sys_conf_clkser_vcodivide,
103 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
104 OUT_DIVIDE => sys_conf_clkser_outdivide)
105 port map (
106 CLKIN => CLKOSC,
107 CLKFX => CLKCOM,
108 LOCKED => open
109 );
110
111 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
112
113 TBCORE : entity work.tbcore_rlink
114 port map (
115 CLK => CLKCOM,
116 RX_DATA => TXDATA,
117 RX_VAL => TXENA,
118 RX_HOLD => TXBUSY,
119 TX_DATA => RXDATA,
120 TX_ENA => RXVAL
121 );
122
123 N4CORE : entity work.tb_nexys4_core
124 port map (
125 I_SWI => I_SWI,
126 I_BTN => I_BTN,
128 );
129
130 UUT : nexys4_aif
131 port map (
132 I_CLK100 => CLKOSC,
133 I_RXD => I_RXD,
134 O_TXD => O_TXD,
135 O_RTS_N => O_RTS_N,
136 I_CTS_N => I_CTS_N,
137 I_SWI => I_SWI,
138 I_BTN => I_BTN,
139 I_BTNRST_N => I_BTNRST_N,
140 O_LED => O_LED,
141 O_RGBLED0 => O_RGBLED0,
142 O_RGBLED1 => O_RGBLED1,
143 O_ANO_N => O_ANO_N,
144 O_SEG_N => O_SEG_N
145 );
146
147 SERMSTR : entity work.serport_master_tb
148 generic map (
149 CDWIDTH => CLKDIV'length)
150 port map (
151 CLK => CLKCOM,
152 RESET => RESET,
153 CLKDIV => CLKDIV,
155 ENAESC => '0',
156 RXDATA => RXDATA,
157 RXVAL => RXVAL,
158 RXERR => RXERR,
159 RXOK => '1',
160 TXDATA => TXDATA,
161 TXENA => TXENA,
162 TXBUSY => TXBUSY,
163 RXSD => O_TXD,
164 TXSD => I_RXD,
165 RXRTS_N => I_CTS_N,
167 );
168
169 proc_moni: process
170 variable oline : line;
171 begin
172
173 loop
174 wait until rising_edge(CLKCOM);
175
176 if RXERR = '1' then
177 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
178 writeline(output, oline);
179 end if;
180
181 end loop;
182
183 end process proc_moni;
184
185 proc_simbus: process (SB_VAL)
186 begin
187 if SB_VAL'event and to_x01(SB_VAL)='1' then
188 if SB_ADDR = sbaddr_portsel then
189 R_PORTSEL_XON <= to_x01(SB_DATA(1));
190 end if;
191 end if;
192 end process proc_simbus;
193
194end sim;
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' RXERR
Definition: tb_nexys4.vhd:64
slbit := '0' RESET
Definition: tb_nexys4.vhd:60
slv8 :=( others => '0') O_SEG_N
Definition: tb_nexys4.vhd:81
integer := 0 CLKCOM_CYCLE
Definition: tb_nexys4.vhd:58
slbit := '1' I_BTNRST_N
Definition: tb_nexys4.vhd:76
Delay_length := 10 ns clock_period
Definition: tb_nexys4.vhd:87
slv2 := "00" CLKDIV
Definition: tb_nexys4.vhd:61
slv16 :=( others => '0') O_LED
Definition: tb_nexys4.vhd:77
slbit := '0' TXENA
Definition: tb_nexys4.vhd:67
slv8 :=( others => '0') RXDATA
Definition: tb_nexys4.vhd:62
Delay_length := 200 ns clock_offset
Definition: tb_nexys4.vhd:88
slbit := '0' RXACT
Definition: tb_nexys4.vhd:65
slv5 :=( others => '0') I_BTN
Definition: tb_nexys4.vhd:75
slbit := '0' RXVAL
Definition: tb_nexys4.vhd:63
slbit := '1' O_TXD
Definition: tb_nexys4.vhd:71
slbit := '0' I_CTS_N
Definition: tb_nexys4.vhd:73
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
Definition: tb_nexys4.vhd:85
slv3 :=( others => '0') O_RGBLED1
Definition: tb_nexys4.vhd:79
slbit := '0' CLKOSC
Definition: tb_nexys4.vhd:55
slbit := '0' O_RTS_N
Definition: tb_nexys4.vhd:72
slbit := '0' CLKCOM
Definition: tb_nexys4.vhd:56
slv8 :=( others => '0') O_ANO_N
Definition: tb_nexys4.vhd:80
slbit := '0' TXBUSY
Definition: tb_nexys4.vhd:68
slv3 :=( others => '0') O_RGBLED0
Definition: tb_nexys4.vhd:78
slbit := '0' R_PORTSEL_XON
Definition: tb_nexys4.vhd:83
slv8 :=( others => '0') TXDATA
Definition: tb_nexys4.vhd:66
slv16 :=( others => '0') I_SWI
Definition: tb_nexys4.vhd:74
slbit := '1' I_RXD
Definition: tb_nexys4.vhd:70
out I_BTNRST_N slbit
out I_SWI slv16
Definition: xlib.vhd:35