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W11 CPU core and support modules
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tb_nexys4d.vhd
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1-- $Id: tb_nexys4d.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys4d - sim
7-- Description: Test bench for nexys4d (base)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_nexys4d_core
14-- serport/tb/serport_master_tb
15-- nexys4d_aif [UUT]
16--
17-- To test: generic, any nexys4d_aif target
18--
19-- Target Devices: generic
20-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
25-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4)
26------------------------------------------------------------------------------
27
28library ieee;
29use ieee.std_logic_1164.all;
30use ieee.numeric_std.all;
31use ieee.std_logic_textio.all;
32use std.textio.all;
33
34use work.slvtypes.all;
35use work.rlinklib.all;
36use work.xlib.all;
37use work.nexys4dlib.all;
38use work.simlib.all;
39use work.simbus.all;
40use work.sys_conf.all;
41
42entity tb_nexys4d is
43end tb_nexys4d;
44
45architecture sim of tb_nexys4d is
46
47 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
48 signal CLKCOM : slbit := '0'; -- communication clock
49
50 signal CLKCOM_CYCLE : integer := 0;
51
52 signal RESET : slbit := '0';
53 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
54 signal RXDATA : slv8 := (others=>'0');
55 signal RXVAL : slbit := '0';
56 signal RXERR : slbit := '0';
57 signal RXACT : slbit := '0';
58 signal TXDATA : slv8 := (others=>'0');
59 signal TXENA : slbit := '0';
60 signal TXBUSY : slbit := '0';
61
62 signal I_RXD : slbit := '1';
63 signal O_TXD : slbit := '1';
64 signal O_RTS_N : slbit := '0';
65 signal I_CTS_N : slbit := '0';
66 signal I_SWI : slv16 := (others=>'0');
67 signal I_BTN : slv5 := (others=>'0');
68 signal I_BTNRST_N : slbit := '1';
69 signal O_LED : slv16 := (others=>'0');
70 signal O_RGBLED0 : slv3 := (others=>'0');
71 signal O_RGBLED1 : slv3 := (others=>'0');
72 signal O_ANO_N : slv8 := (others=>'0');
73 signal O_SEG_N : slv8 := (others=>'0');
74
75 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
76
77 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
78
79 constant clock_period : Delay_length := 10 ns;
80 constant clock_offset : Delay_length := 200 ns;
81
82begin
83
84 CLKGEN : simclk
85 generic map (
88 port map (
89 CLK => CLKOSC
90 );
91
92 CLKGEN_COM : sfs_gsim_core
93 generic map (
94 VCO_DIVIDE => sys_conf_clkser_vcodivide,
95 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
96 OUT_DIVIDE => sys_conf_clkser_outdivide)
97 port map (
98 CLKIN => CLKOSC,
99 CLKFX => CLKCOM,
100 LOCKED => open
101 );
102
103 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
104
105 TBCORE : entity work.tbcore_rlink
106 port map (
107 CLK => CLKCOM,
108 RX_DATA => TXDATA,
109 RX_VAL => TXENA,
110 RX_HOLD => TXBUSY,
111 TX_DATA => RXDATA,
112 TX_ENA => RXVAL
113 );
114
115 N4CORE : entity work.tb_nexys4d_core
116 port map (
117 I_SWI => I_SWI,
118 I_BTN => I_BTN,
120 );
121
122 UUT : nexys4d_aif
123 port map (
124 I_CLK100 => CLKOSC,
125 I_RXD => I_RXD,
126 O_TXD => O_TXD,
127 O_RTS_N => O_RTS_N,
128 I_CTS_N => I_CTS_N,
129 I_SWI => I_SWI,
130 I_BTN => I_BTN,
131 I_BTNRST_N => I_BTNRST_N,
132 O_LED => O_LED,
133 O_RGBLED0 => O_RGBLED0,
134 O_RGBLED1 => O_RGBLED1,
135 O_ANO_N => O_ANO_N,
136 O_SEG_N => O_SEG_N
137 );
138
139 SERMSTR : entity work.serport_master_tb
140 generic map (
141 CDWIDTH => CLKDIV'length)
142 port map (
143 CLK => CLKCOM,
144 RESET => RESET,
145 CLKDIV => CLKDIV,
147 ENAESC => '0',
148 RXDATA => RXDATA,
149 RXVAL => RXVAL,
150 RXERR => RXERR,
151 RXOK => '1',
152 TXDATA => TXDATA,
153 TXENA => TXENA,
154 TXBUSY => TXBUSY,
155 RXSD => O_TXD,
156 TXSD => I_RXD,
157 RXRTS_N => I_CTS_N,
159 );
160
161 proc_moni: process
162 variable oline : line;
163 begin
164
165 loop
166 wait until rising_edge(CLKCOM);
167
168 if RXERR = '1' then
169 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
170 writeline(output, oline);
171 end if;
172
173 end loop;
174
175 end process proc_moni;
176
177 proc_simbus: process (SB_VAL)
178 begin
179 if SB_VAL'event and to_x01(SB_VAL)='1' then
180 if SB_ADDR = sbaddr_portsel then
181 R_PORTSEL_XON <= to_x01(SB_DATA(1));
182 end if;
183 end if;
184 end process proc_simbus;
185
186end sim;
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' RXERR
Definition: tb_nexys4d.vhd:56
slbit := '0' RESET
Definition: tb_nexys4d.vhd:52
slv8 :=( others => '0') O_SEG_N
Definition: tb_nexys4d.vhd:73
integer := 0 CLKCOM_CYCLE
Definition: tb_nexys4d.vhd:50
slbit := '1' I_BTNRST_N
Definition: tb_nexys4d.vhd:68
Delay_length := 10 ns clock_period
Definition: tb_nexys4d.vhd:79
slv2 := "00" CLKDIV
Definition: tb_nexys4d.vhd:53
slv16 :=( others => '0') O_LED
Definition: tb_nexys4d.vhd:69
slbit := '0' TXENA
Definition: tb_nexys4d.vhd:59
slv8 :=( others => '0') RXDATA
Definition: tb_nexys4d.vhd:54
Delay_length := 200 ns clock_offset
Definition: tb_nexys4d.vhd:80
slbit := '0' RXACT
Definition: tb_nexys4d.vhd:57
slv5 :=( others => '0') I_BTN
Definition: tb_nexys4d.vhd:67
slbit := '0' RXVAL
Definition: tb_nexys4d.vhd:55
slbit := '1' O_TXD
Definition: tb_nexys4d.vhd:63
slbit := '0' I_CTS_N
Definition: tb_nexys4d.vhd:65
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
Definition: tb_nexys4d.vhd:77
slv3 :=( others => '0') O_RGBLED1
Definition: tb_nexys4d.vhd:71
slbit := '0' CLKOSC
Definition: tb_nexys4d.vhd:47
slbit := '0' O_RTS_N
Definition: tb_nexys4d.vhd:64
slbit := '0' CLKCOM
Definition: tb_nexys4d.vhd:48
slv8 :=( others => '0') O_ANO_N
Definition: tb_nexys4d.vhd:72
slbit := '0' TXBUSY
Definition: tb_nexys4d.vhd:60
slv3 :=( others => '0') O_RGBLED0
Definition: tb_nexys4d.vhd:70
slbit := '0' R_PORTSEL_XON
Definition: tb_nexys4d.vhd:75
slv8 :=( others => '0') TXDATA
Definition: tb_nexys4d.vhd:58
slv16 :=( others => '0') I_SWI
Definition: tb_nexys4d.vhd:66
slbit := '1' I_RXD
Definition: tb_nexys4d.vhd:62
out I_BTNRST_N slbit
Definition: xlib.vhd:35