28use ieee.std_logic_1164.
all;
29use ieee.numeric_std.
all;
30use ieee.std_logic_textio.
all;
125 UUT : nexys4d_dram_aif
179 variable oline : line;
183 wait until rising_edge(CLKCOM);
187 writeline(output, oline);
192 end process proc_moni;
194 proc_simbus:
process (SB_VAL)
196 if SB_VAL'event and to_x01(SB_VAL)='1' then
201 end process proc_simbus;
in CLKDIV slv( CDWIDTH- 1 downto 0)
VCO_MULTIPLY positive := 1
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
Delay_length := 10 ns clock_period
slv16 :=( others => '0') O_LED
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slv2 :=( others => 'Z') IO_DDR2_DQS_P
slv2 :=( others => 'Z') IO_DDR2_DQS_N
slv16 :=( others => 'Z') IO_DDR2_DQ
slv5 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED1
slv8 :=( others => '0') O_ANO_N
slv3 :=( others => '0') O_RGBLED0
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TXDATA
slv16 :=( others => '0') I_SWI