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W11 CPU core and support modules
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tb_nexys4d_dram.vhd
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1-- $Id: tb_nexys4d_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys4d_dram - sim
7-- Description: Test bench for nexys4d (base+dram)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_nexys4d_core
14-- serport/tb/serport_master_tb
15-- nexys4d_dram_aif [UUT]
16--
17-- To test: generic, any nexys4d_dram_aif target
18--
19-- Target Devices: generic
20-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2018-12-30 1099 1.0 Initial version (derived from tb_nexys4)
25------------------------------------------------------------------------------
26
27library ieee;
28use ieee.std_logic_1164.all;
29use ieee.numeric_std.all;
30use ieee.std_logic_textio.all;
31use std.textio.all;
32
33use work.slvtypes.all;
34use work.rlinklib.all;
35use work.xlib.all;
36use work.nexys4dlib.all;
37use work.simlib.all;
38use work.simbus.all;
39use work.sys_conf.all;
40
43
44architecture sim of tb_nexys4d_dram is
45
46 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
47 signal CLKCOM : slbit := '0'; -- communication clock
48
49 signal CLKCOM_CYCLE : integer := 0;
50
51 signal RESET : slbit := '0';
52 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
53 signal RXDATA : slv8 := (others=>'0');
54 signal RXVAL : slbit := '0';
55 signal RXERR : slbit := '0';
56 signal RXACT : slbit := '0';
57 signal TXDATA : slv8 := (others=>'0');
58 signal TXENA : slbit := '0';
59 signal TXBUSY : slbit := '0';
60
61 signal I_RXD : slbit := '1';
62 signal O_TXD : slbit := '1';
63 signal O_RTS_N : slbit := '0';
64 signal I_CTS_N : slbit := '0';
65 signal I_SWI : slv16 := (others=>'0');
66 signal I_BTN : slv5 := (others=>'0');
67 signal I_BTNRST_N : slbit := '1';
68 signal O_LED : slv16 := (others=>'0');
69 signal O_RGBLED0 : slv3 := (others=>'0');
70 signal O_RGBLED1 : slv3 := (others=>'0');
71 signal O_ANO_N : slv8 := (others=>'0');
72 signal O_SEG_N : slv8 := (others=>'0');
73
74 signal IO_DDR2_DQ : slv16 := (others=>'Z');
75 signal IO_DDR2_DQS_P : slv2 := (others=>'Z');
76 signal IO_DDR2_DQS_N : slv2 := (others=>'Z');
77
78 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
79
80 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
81
82 constant clock_period : Delay_length := 10 ns;
83 constant clock_offset : Delay_length := 200 ns;
84
85begin
86
87 CLKGEN : simclk
88 generic map (
91 port map (
92 CLK => CLKOSC
93 );
94
95 CLKGEN_COM : sfs_gsim_core
96 generic map (
97 VCO_DIVIDE => sys_conf_clkser_vcodivide,
98 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
99 OUT_DIVIDE => sys_conf_clkser_outdivide)
100 port map (
101 CLKIN => CLKOSC,
102 CLKFX => CLKCOM,
103 LOCKED => open
104 );
105
106 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
107
108 TBCORE : entity work.tbcore_rlink
109 port map (
110 CLK => CLKCOM,
111 RX_DATA => TXDATA,
112 RX_VAL => TXENA,
113 RX_HOLD => TXBUSY,
114 TX_DATA => RXDATA,
115 TX_ENA => RXVAL
116 );
117
118 N4CORE : entity work.tb_nexys4d_core
119 port map (
120 I_SWI => I_SWI,
121 I_BTN => I_BTN,
123 );
124
125 UUT : nexys4d_dram_aif
126 port map (
127 I_CLK100 => CLKOSC,
128 I_RXD => I_RXD,
129 O_TXD => O_TXD,
130 O_RTS_N => O_RTS_N,
131 I_CTS_N => I_CTS_N,
132 I_SWI => I_SWI,
133 I_BTN => I_BTN,
134 I_BTNRST_N => I_BTNRST_N,
135 O_LED => O_LED,
136 O_RGBLED0 => O_RGBLED0,
137 O_RGBLED1 => O_RGBLED1,
138 O_ANO_N => O_ANO_N,
139 O_SEG_N => O_SEG_N,
140 DDR2_DQ => IO_DDR2_DQ,
141 DDR2_DQS_P => IO_DDR2_DQS_P,
142 DDR2_DQS_N => IO_DDR2_DQS_N,
143 DDR2_ADDR => open,
144 DDR2_BA => open,
145 DDR2_RAS_N => open,
146 DDR2_CAS_N => open,
147 DDR2_WE_N => open,
148 DDR2_CK_P => open,
149 DDR2_CK_N => open,
150 DDR2_CKE => open,
151 DDR2_CS_N => open,
152 DDR2_DM => open,
153 DDR2_ODT => open
154 );
155
156 SERMSTR : entity work.serport_master_tb
157 generic map (
158 CDWIDTH => CLKDIV'length)
159 port map (
160 CLK => CLKCOM,
161 RESET => RESET,
162 CLKDIV => CLKDIV,
164 ENAESC => '0',
165 RXDATA => RXDATA,
166 RXVAL => RXVAL,
167 RXERR => RXERR,
168 RXOK => '1',
169 TXDATA => TXDATA,
170 TXENA => TXENA,
171 TXBUSY => TXBUSY,
172 RXSD => O_TXD,
173 TXSD => I_RXD,
174 RXRTS_N => I_CTS_N,
176 );
177
178 proc_moni: process
179 variable oline : line;
180 begin
181
182 loop
183 wait until rising_edge(CLKCOM);
184
185 if RXERR = '1' then
186 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
187 writeline(output, oline);
188 end if;
189
190 end loop;
191
192 end process proc_moni;
193
194 proc_simbus: process (SB_VAL)
195 begin
196 if SB_VAL'event and to_x01(SB_VAL)='1' then
197 if SB_ADDR = sbaddr_portsel then
198 R_PORTSEL_XON <= to_x01(SB_DATA(1));
199 end if;
200 end if;
201 end process proc_simbus;
202
203end sim;
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
out I_BTNRST_N slbit
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
slbit := '1' I_BTNRST_N
Delay_length := 10 ns clock_period
slv16 :=( others => '0') O_LED
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slv2 :=( others => 'Z') IO_DDR2_DQS_P
slv2 :=( others => 'Z') IO_DDR2_DQS_N
slv16 :=( others => 'Z') IO_DDR2_DQ
slv5 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED1
slv8 :=( others => '0') O_ANO_N
slv3 :=( others => '0') O_RGBLED0
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TXDATA
slv16 :=( others => '0') I_SWI
Definition: xlib.vhd:35