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W11 CPU core and support modules
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tb_tst_serloop1_n4d.vhd
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1-- $Id: tb_tst_serloop1_n4d.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_tst_serloop1_n4d - sim
7-- Description: Test bench for sys_tst_serloop1_n4d
8--
9-- Dependencies: simlib/simclk
10-- xlib/sfs_gsim_core
11-- sys_tst_serloop1_n4d [UUT]
12-- tb/tb_tst_serloop
13--
14-- To test: sys_tst_serloop1_n4d
15--
16-- Target Devices: generic
17--
18-- Revision History:
19-- Date Rev Version Comment
20-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
21-- 2017-01-04 838 1.0 Initial version (cloned from tb_tst_serloop1_n4)
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26use ieee.numeric_std.all;
27use ieee.std_logic_textio.all;
28use std.textio.all;
29
30use work.slvtypes.all;
31use work.xlib.all;
32use work.simlib.all;
33use work.sys_conf.all;
34
37
38architecture sim of tb_tst_serloop1_n4d is
39
40 signal CLK100 : slbit := '0';
41
42 signal CLK : slbit := '0';
43
44 signal I_RXD : slbit := '1';
45 signal O_TXD : slbit := '1';
46 signal O_RTS_N : slbit := '0';
47 signal I_CTS_N : slbit := '0';
48 signal I_SWI : slv16 := (others=>'0');
49 signal I_BTN : slv5 := (others=>'0');
50
51 signal RXD : slbit := '1';
52 signal TXD : slbit := '1';
53 signal RTS_N : slbit := '0';
54 signal CTS_N : slbit := '0';
55 signal SWI : slv16 := (others=>'0');
56 signal BTN : slv5 := (others=>'0');
57
58 constant clock_period : Delay_length := 10 ns;
59 constant clock_offset : Delay_length := 200 ns;
60 constant delay_time : Delay_length := 2 ns;
61
62begin
63
64 SYSCLK : simclk
65 generic map (
68 port map (
69 CLK => CLK100
70 );
71
72 GEN_CLKSYS : sfs_gsim_core
73 generic map (
74 VCO_DIVIDE => sys_conf_clksys_vcodivide,
75 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
76 OUT_DIVIDE => sys_conf_clksys_outdivide)
77 port map (
78 CLKIN => CLK100,
79 CLKFX => CLK,
80 LOCKED => open
81 );
82
83 UUT : entity work.sys_tst_serloop1_n4d
84 port map (
86 I_RXD => I_RXD,
87 O_TXD => O_TXD,
90 I_SWI => I_SWI,
91 I_BTN => I_BTN,
92 I_BTNRST_N => '1',
93 O_LED => open,
94 O_RGBLED0 => open,
95 O_RGBLED1 => open,
96 O_ANO_N => open,
97 O_SEG_N => open
98 );
99
100 GENTB : entity work.tb_tst_serloop
101 port map (
102 CLKS => CLK,
103 CLKH => CLK,
104 P0_RXD => RXD,
105 P0_TXD => TXD,
106 P0_RTS_N => RTS_N,
107 P0_CTS_N => CTS_N,
108 P1_RXD => open, -- port 1 unused for n4d !
109 P1_TXD => '0',
110 P1_RTS_N => '0',
111 P1_CTS_N => open,
112 SWI => SWI(7 downto 0),
113 BTN => BTN(3 downto 0)
114 );
115
116 I_RXD <= RXD after delay_time;
117 TXD <= O_TXD after delay_time;
118 RTS_N <= O_RTS_N after delay_time;
119 I_CTS_N <= CTS_N after delay_time;
120
121 I_SWI <= SWI after delay_time;
122 I_BTN <= BTN after delay_time;
123
124end sim;
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
Delay_length := 2 ns delay_time
Delay_length := 10 ns clock_period
slv16 :=( others => '0') SWI
Delay_length := 200 ns clock_offset
slv5 :=( others => '0') I_BTN
slv5 :=( others => '0') BTN
slv16 :=( others => '0') I_SWI
out P0_RXD slbit
in P1_RTS_N slbit
in P1_TXD slbit
in P0_TXD slbit
out P0_CTS_N slbit
out P1_RXD slbit
in P0_RTS_N slbit
out P1_CTS_N slbit
Definition: xlib.vhd:35