29use ieee.std_logic_1164.
all;
30use ieee.numeric_std.
all;
31use ieee.std_logic_textio.
all;
138 variable eff_txd : slbit := '0';
162 end process proc_port_mux;
165 variable cts_timer : integer := 0;
168 if rising_edge(CLKS) then
174 if cts_timer>0 and cts_timer<CTS_CYCLE then
175 cts_timer := cts_timer - 1;
180 if cts_timer < cts_fract then
189 end process proc_cts;
192 variable xon_timer : integer := 0;
194 if rising_edge(CLKS) then
200 if xon_timer>0 and xon_timer<XON_CYCLE then
201 xon_timer := xon_timer - 1;
206 if xon_timer < xon_fract then
214 end process proc_xonrxok;
218 if rising_edge(CLKS) then
225 end process proc_xontxok;
228 file fstim : text open read_mode is "tb_tst_serloop_stim";
229 variable iline : line;
230 variable oline : line;
231 variable idelta : integer := 0;
232 variable iactport : slbit := '0';
233 variable iswi : slv8 := (others=>'0');
234 variable btn_num : integer := 0;
235 variable i_cycle : integer := 0;
236 variable i_fract : integer := 0;
237 variable nbyte : integer := 0;
238 variable enaesc : slbit := '0';
239 variable enaxon : slbit := '0';
240 variable bcnt : integer := 0;
241 variable itxdata : slv8 := (others=>'0');
242 variable ok : boolean;
243 variable dname : string(1 to 6) := (others=>' ');
247 for i in 1 to ncyc loop
248 wait until rising_edge(CLKS);
250 end procedure waitclk;
255 SWI <= (others=>'0');
256 BTN <= (others=>'0');
258 wait until rising_edge(CLKS);
260 file_loop: while not endfile(fstim) loop
262 readline (fstim, iline);
264 readcomment(iline, ok);
265 next file_loop when ok;
267 readword(iline, dname, ok);
271 read_ea(iline, idelta);
272 writetimestamp(oline, CLK_CYCLE, ": wait ");
273 write(oline, idelta, right, 5);
274 writeline(output, oline);
278 read_ea(iline, iactport);
280 writetimestamp(oline, CLK_CYCLE, ": port ");
281 write(oline, iactport, right, 5);
282 writeline(output, oline);
285 read_ea(iline, i_cycle);
286 read_ea(iline, i_fract);
289 writetimestamp(oline, CLK_CYCLE, ": cts ");
290 write(oline, i_cycle, right, 5);
291 write(oline, i_fract, right, 5);
292 writeline(output, oline);
295 read_ea(iline, i_cycle);
296 read_ea(iline, i_fract);
299 writetimestamp(oline, CLK_CYCLE, ": cts ");
300 write(oline, i_cycle, right, 5);
301 write(oline, i_fract, right, 5);
302 writeline(output, oline);
305 read_ea(iline, iswi);
306 read_ea(iline, idelta);
307 writetimestamp(oline, CLK_CYCLE, ": swi ");
308 write(oline, iswi, right, 10);
309 write(oline, idelta, right, 5);
310 writeline(output, oline);
311 wait until rising_edge(CLKH);
313 wait until rising_edge(CLKS);
317 read_ea(iline, btn_num);
318 read_ea(iline, idelta);
319 if btn_num>=0 and btn_num<=3 then
320 writetimestamp(oline, CLK_CYCLE, ": btn ");
321 write(oline, btn_num, right, 5);
322 write(oline, idelta, right, 5);
323 writeline(output, oline);
324 wait until rising_edge(CLKH);
326 wait until rising_edge(CLKH);
327 wait until rising_edge(CLKH);
328 wait until rising_edge(CLKH);
330 wait until rising_edge(CLKH);
331 wait until rising_edge(CLKH);
332 wait until rising_edge(CLKH);
333 wait until rising_edge(CLKS);
336 write(oline, string'("!! btn: btn number out of range"));
337 writeline(output, oline);
341 read_ea(iline, nbyte);
342 read_ea(iline, enaesc);
343 read_ea(iline, enaxon);
344 writetimestamp(oline, CLK_CYCLE, ": expect");
345 write(oline, nbyte, right, 5);
346 write(oline, enaesc, right, 3);
347 write(oline, enaxon, right, 3);
348 writeline(output, oline);
358 wait until rising_edge(CLKS);
361 read_ea(iline, nbyte);
362 read_ea(iline, enaesc);
363 read_ea(iline, enaxon);
364 writetimestamp(oline, CLK_CYCLE, ": send ");
365 write(oline, nbyte, right, 5);
366 write(oline, enaesc, right, 3);
367 write(oline, enaxon, right, 3);
368 writeline(output, oline);
370 itxdata := (others=>'0');
372 wait until falling_edge(CLKS);
373 while bcnt < nbyte loop
375 wait until falling_edge(CLKS);
379 itxdata := slv(unsigned(itxdata) + 1);
383 wait until falling_edge(CLKS);
385 wait until falling_edge(CLKS);
388 wait until falling_edge(CLKS);
390 wait until rising_edge(CLKS);
393 read_ea(iline, idelta);
394 writetimestamp(oline, CLK_CYCLE, ": break ");
395 write(oline, idelta, right, 5);
396 writeline(output, oline);
402 waitclk(3*to_integer(unsigned(CLKDIV)+1));
404 wait until falling_edge(CLKS);
407 wait until falling_edge(CLKS);
409 wait until rising_edge(CLKS);
412 read_ea(iline, idelta);
413 writetimestamp(oline, CLK_CYCLE, ": clkdiv");
414 write(oline, idelta, right, 5);
415 writeline(output, oline);
418 wait until rising_edge(CLKS);
422 write(oline, string'("?? unknown command: "));
424 writeline(output, oline);
425 report "aborting" severity failure;
429 report "failed to find command" severity failure;
438 waitclk(20*(to_integer(unsigned(CLKDIV))+1));
440 writetimestamp(oline, CLK_CYCLE, ": DONE ");
441 writeline(output, oline);
445 report "Simulation Finished" severity failure;
447 end process proc_stim;
450 variable oline : line;
451 variable dclk : integer := 0;
452 variable active_1 : slbit := '0';
453 variable irxdata : slv8 := (others=>'0');
454 variable irxeff : slv8 := (others=>'0');
455 variable irxval : slbit := '0';
456 variable doesc : slbit := '0';
457 variable bcnt : integer := 0;
458 variable xseen : slbit := '0';
462 wait until falling_edge(CLKS);
468 irxdata := (others=>'0');
474 writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
476 writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
477 write(oline, bcnt, right, 5);
478 write(oline, string'(" expect="));
481 writeline(output, oline);
487 writetimestamp(oline, CLK_CYCLE, ": char: ");
488 write(oline, RXDATA, right, 10);
489 write(oline, string'(" ("));
490 writeoct(oline, RXDATA, right, 3);
491 write(oline, string'(") dt="));
492 write(oline, dclk, right, 4);
500 write(oline, string'(" eff="));
501 write(oline, irxeff, right, 10);
502 write(oline, string'(" ("));
503 writeoct(oline, irxeff, right, 3);
504 write(oline, string'(")"));
508 write(oline, string'(" XESC seen"));
513 if RXDATA = c_serport_xon then
514 write(oline, string'(" XON seen"));
517 elsif RXDATA = c_serport_xoff then
518 write(oline, string'(" XOFF seen"));
524 if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
525 if irxeff = irxdata then
526 write(oline, string'(" OK"));
528 write(oline, string'(" FAIL: expect="));
529 write(oline, irxdata, right, 10);
531 irxdata := slv(unsigned(irxdata) + 1);
535 writeline(output, oline);
541 writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
542 writeline(output, oline);
549 end process proc_moni;
in CLKDIV slv( CDWIDTH- 1 downto 0)
std_logic_vector( 12 downto 0) slv13
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 7 downto 0) slv8
slv8 :=( others => '0') UART_TXDATA
slv8 :=( others => '0') RXDATA
slv13 :=( others => '0') CLKDIV
slv8 :=( others => '0') TXDATA
slbit := '0' M2S_XOFFSEEN