27use ieee.std_logic_1164.
all;
28use ieee.numeric_std.
all;
151 G2B_WW :
gray2bin_gen -- gray->bin
for waddr
on write side
152 generic map (DWIDTH =>
AWIDTH)
154 G2B_WR :
gray2bin_gen -- gray->bin
for waddr
on read side
155 generic map (DWIDTH =>
AWIDTH)
157 G2B_RR :
gray2bin_gen -- gray->bin
for raddr
on read side
158 generic map (DWIDTH =>
AWIDTH)
160 G2B_RW :
gray2bin_gen -- gray->bin
for raddr
on write side
161 generic map (DWIDTH =>
AWIDTH)
169 if rising_edge(CLKW) then
180 end process proc_regw;
185 variable ibusy : slbit := '0';
186 variable irstw : slbit := '0';
187 variable igcw_ce : slbit := '0';
188 variable igcw_rst : slbit := '0';
189 variable isizew : slv(a_range) := (others=>'0');
197 if unsigned(isizew) = 0 then
203 if unsigned(isizew) = 1 then
225 isizew := (others=>'1');
237 end process proc_nextw;
244 if rising_edge(CLKR) then
255 end process proc_regr;
260 variable ival : slbit := '0';
261 variable irstr : slbit := '0';
262 variable igcr_ce : slbit := '0';
263 variable igcr_rst : slbit := '0';
264 variable isizer : slv(a_range) := (others=>'0');
273 if unsigned(isizer) = 0 then
279 if unsigned(isizer) = 1 then
301 isizer := (others=>'0');
313 end process proc_nextr;
slv( a_range ) :=( others => '0') NW_SIZEW
slv( AWIDTH- 1 downto 0) :=( others => '0') WADDR
slv( AWIDTH- 1 downto 0) :=( others => '0') WADDR_BIN_W
slbit := '0' RW_RSTW_E_S1
slv( a_range ) :=( others => '0') RR_WADDR_S1
slv( a_range ) :=( others => '0') RW_RADDR_S0
slv( a_range ) :=( others => '0') RR_SIZER
slbit := '0' RR_RSTR_E_S0
slv( a_range ) :=( others => '0') NR_SIZER
integer range AWIDTH- 1 downto 0 a_range
slv( AWIDTH- 1 downto 0) :=( others => '0') RADDR
slv( AWIDTH- 1 downto 0) :=( others => '0') WADDR_BIN_R
slbit := '0' RR_RSTR_E_S1
slv( AWIDTH- 1 downto 0) :=( others => '0') RADDR_BIN_W
slv( a_range ) :=( others => '0') RR_WADDR_S0
slv( AWIDTH- 1 downto 0) :=( others => '0') RADDR_BIN_R
slv( a_range ) :=( others => '0') RW_RADDR_S1
slbit := '0' RW_RSTW_E_S0
slv( a_range ) :=( others => '0') RW_SIZEW
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
out SIZER slv( AWIDTH- 1 downto 0)
out SIZEW slv( AWIDTH- 1 downto 0)