22use ieee.std_logic_1164.
all;
23use ieee.numeric_std.
all;
79 DIA => EM_MREQ.din
(7 downto 0),
98 DIA => EM_MREQ.din
(15 downto 8),
107 if rising_edge(CLK) then
115 end process proc_regs;
regs_type := regs_init N_REGS
slv( AWIDTH- 1 downto 1) :=( others => '0') addrzero
regs_type :=( '0', '0',( others => '0'), addrzero) regs_init
regs_type := regs_init R_REGS
slv16 :=( others => '0') MEM_DOA
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 1 downto 0) slv2