w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_bram.vhd
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1-- $Id: pdp11_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_bram - syn
7-- Description: pdp11: BRAM based ext. memory dummy
8--
9-- Dependencies: memlib/ram_2swsr_rfirst_gen
10-- Test bench: -
11-- Target Devices: generic
12-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
13-- Revision History:
14-- Date Rev Version Comment
15-- 2011-11-18 427 1.0.3 now numeric_std clean
16-- 2008-03-01 120 1.0.2 add addrzero constant to avoid XST errors
17-- 2008-02-23 118 1.0.1 AWIDTH now a generic port
18-- 2008-02-17 117 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23use ieee.numeric_std.all;
24
25use work.slvtypes.all;
26use work.memlib.all;
27use work.pdp11.all;
28
29entity pdp11_bram is -- cache
30 generic (
31 AWIDTH : positive := 14); -- address width
32 port (
33 CLK : in slbit; -- clock
34 GRESET : in slbit; -- general reset
35 EM_MREQ : in em_mreq_type; -- em request
36 EM_SRES : out em_sres_type -- em response
37 );
38end pdp11_bram;
39
40
41architecture syn of pdp11_bram is
42
43 type regs_type is record
44 req_r : slbit; -- read request
45 req_w : slbit; -- write request
46 be : slv2; -- byte enables
47 addr : slv(AWIDTH-1 downto 1); -- address
48 end record regs_type;
49
50 constant addrzero : slv(AWIDTH-1 downto 1) := (others=>'0');
51
52 constant regs_init : regs_type := (
53 '0','0', -- req_r,w
54 (others=>'0'), -- be
55 addrzero -- addr
56 );
57
58 signal R_REGS : regs_type := regs_init; -- state registers
59 signal N_REGS : regs_type := regs_init; -- next value state regs
60
61 signal MEM_ENB : slbit := '0';
62 signal MEM_WEA : slv2 := "00";
63 signal MEM_DOA : slv16 := (others=>'0');
64begin
65
66 MEM_BYT0 : ram_2swsr_rfirst_gen
67 generic map (
68 AWIDTH => AWIDTH-1,
69 DWIDTH => 8)
70 port map (
71 CLKA => CLK,
72 CLKB => CLK,
73 ENA => EM_MREQ.req,
74 ENB => MEM_ENB,
75 WEA => MEM_WEA(0),
76 WEB => R_REGS.be(0),
77 ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
78 ADDRB => R_REGS.addr,
79 DIA => EM_MREQ.din(7 downto 0),
80 DIB => MEM_DOA(7 downto 0),
81 DOA => MEM_DOA(7 downto 0),
82 DOB => open
83 );
84
85 MEM_BYT1 : ram_2swsr_rfirst_gen
86 generic map (
87 AWIDTH => AWIDTH-1,
88 DWIDTH => 8)
89 port map (
90 CLKA => CLK,
91 CLKB => CLK,
92 ENA => EM_MREQ.req,
93 ENB => MEM_ENB,
94 WEA => MEM_WEA(1),
95 WEB => R_REGS.be(1),
96 ADDRA => EM_MREQ.addr(AWIDTH-1 downto 1),
97 ADDRB => R_REGS.addr,
98 DIA => EM_MREQ.din(15 downto 8),
99 DIB => MEM_DOA(15 downto 8),
100 DOA => MEM_DOA(15 downto 8),
101 DOB => open
102 );
103
104 proc_regs: process (CLK)
105 begin
106
107 if rising_edge(CLK) then
108 if GRESET = '1' then
109 R_REGS <= regs_init;
110 else
111 R_REGS <= N_REGS;
112 end if;
113 end if;
114
115 end process proc_regs;
116
117 N_REGS.req_r <= EM_MREQ.req and not EM_MREQ.we;
118 N_REGS.req_w <= EM_MREQ.req and EM_MREQ.we;
119 N_REGS.be <= EM_MREQ.be;
120 N_REGS.addr <= EM_MREQ.addr(N_REGS.addr'range);
121
122 MEM_WEA(0) <= EM_MREQ.we and EM_MREQ.be(0);
123 MEM_WEA(1) <= EM_MREQ.we and EM_MREQ.be(1);
124 MEM_ENB <= EM_MREQ.cancel and R_REGS.req_w;
125
126 EM_SRES.ack_r <= R_REGS.req_r;
127 EM_SRES.ack_w <= R_REGS.req_w;
128 EM_SRES.dout <= MEM_DOA;
129
130end syn;
regs_type := regs_init N_REGS
Definition: pdp11_bram.vhd:59
slbit := '0' MEM_ENB
Definition: pdp11_bram.vhd:61
slv2 := "00" MEM_WEA
Definition: pdp11_bram.vhd:62
slv( AWIDTH- 1 downto 1) :=( others => '0') addrzero
Definition: pdp11_bram.vhd:50
regs_type :=( '0', '0',( others => '0'), addrzero) regs_init
Definition: pdp11_bram.vhd:52
regs_type := regs_init R_REGS
Definition: pdp11_bram.vhd:58
slv16 :=( others => '0') MEM_DOA
Definition: pdp11_bram.vhd:63
AWIDTH positive := 14
Definition: pdp11_bram.vhd:31
in EM_MREQ em_mreq_type
Definition: pdp11_bram.vhd:35
in GRESET slbit
Definition: pdp11_bram.vhd:34
in CLK slbit
Definition: pdp11_bram.vhd:33
out EM_SRES em_sres_type
Definition: pdp11_bram.vhd:37
Definition: pdp11.vhd:123
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31