w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_bram_memctl.vhd
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1-- $Id: pdp11_bram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_bram_memctl - syn
7-- Description: pdp11: BRAM based memctl
8--
9-- Dependencies: ram_1swsr_wfirst_gen
10-- Test bench: -
11-- Target Devices: 7-Series
12-- Tool versions: ise 14.7; viv 2014.4-2016.1; ghdl 0.31-0.33
13--
14-- Revision History:
15-- Date Rev Version Comment
16-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
17-- 2016-03-20 749 1.1 use ram_1swsr_wfirst_gen rather BRAM_SINGLE_MACRO
18-- 2015-02-08 644 1.0 Initial version
19------------------------------------------------------------------------------
20
21library ieee;
22use ieee.std_logic_1164.all;
23use ieee.numeric_std.all;
24
25use work.slvtypes.all;
26use work.memlib.all;
27use work.pdp11.all;
28
29-- ----------------------------------------------------------------------------
30
31entity pdp11_bram_memctl is -- BRAM based memctl
32 generic (
33 MAWIDTH : positive := 4; -- mux address width
34 NBLOCK : positive := 11); -- number of 16 kByte blocks
35 port (
36 CLK : in slbit; -- clock
37 RESET : in slbit; -- reset
38 REQ : in slbit; -- request
39 WE : in slbit; -- write enable
40 BUSY : out slbit; -- controller busy
41 ACK_R : out slbit; -- acknowledge read
42 ACK_W : out slbit; -- acknowledge write
43 ACT_R : out slbit; -- signal active read
44 ACT_W : out slbit; -- signal active write
45 ADDR : in slv20; -- address
46 BE : in slv4; -- byte enable
47 DI : in slv32; -- data in (memory view)
48 DO : out slv32 -- data out (memory view)
49 );
51
52architecture syn of pdp11_bram_memctl is
53
54 type state_type is (
55 s_idle, -- s_idle: wait for req
56 s_read0, -- s_read0
57 s_read1, -- s_read1
58 s_write -- s_write
59 );
60
61 type regs_type is record
62 state : state_type; -- state
63 muxaddr : slv(MAWIDTH-1 downto 0); -- mux addr buffer
64 celladdr : slv12; -- cell addr buffer
65 cellen : slv(2**MAWIDTH-1 downto 0);-- cell enables
66 cellwe : slv4; -- write enables
67 dibuf : slv32; -- data in buffer
68 dobuf : slv32; -- data out buffer
69 ackr : slbit; -- signal ack_r
70 end record regs_type;
71
72 constant muxaddrzero : slv(MAWIDTH-1 downto 0) := (others=>'0');
73 constant cellenzero : slv(2**MAWIDTH-1 downto 0) := (others=>'0');
74 constant regs_init : regs_type := (
75 s_idle, -- state
76 muxaddrzero, -- muxaddr
77 (others=>'0'), -- celladdr
78 cellenzero, -- cellen
79 (others=>'0'), -- cellwe
80 (others=>'0'), -- dibuf
81 (others=>'0'), -- dobuf
82 '0' -- ackr
83 );
84
86 signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
87
88 type mem_do_type is array (NBLOCK-1 downto 0) of slv32;
89 signal MEM_DO : mem_do_type := (others=> (others => '0'));
90
91begin
92
93 assert MAWIDTH <= 8
94 report "assert(MAWIDTH <= 8)" severity failure;
95 assert NBLOCK <= 2**MAWIDTH
96 report "assert(NBLOCK <= 2**MAWIDTH)" severity failure;
97
98 -- generate memory array
99 -- 4 colums, one for each byte of the 32 bit word
100 -- NBLOCK rows, as many as one can afford ...
101
102 MARRAY: for row in NBLOCK-1 downto 0 generate
103 MROW: for col in 3 downto 0 generate
104 begin
106 generic map (
107 AWIDTH => 12, -- 4 Kb blocks
108 DWIDTH => 8) -- byte wide
109 port map (
110 CLK => CLK,
111 EN => R_REGS.cellen(row),
112 WE => R_REGS.cellwe(col),
113 ADDR => R_REGS.celladdr,
114 DI => R_REGS.dibuf(8*col+7 downto 8*col),
115 DO => MEM_DO(row)(8*col+7 downto 8*col)
116 );
117 end generate MROW;
118 end generate MARRAY;
119
120 proc_regs: process (CLK)
121 begin
122
123 if rising_edge(CLK) then
124 if RESET = '1' then
125 R_REGS <= regs_init;
126 else
127 R_REGS <= N_REGS;
128 end if;
129 end if;
130
131 end process proc_regs;
132
133 proc_next: process (R_REGS, ADDR, DI, REQ, WE, BE, MEM_DO)
134
135 variable r : regs_type := regs_init;
136 variable n : regs_type := regs_init;
137 variable ibusy : slbit := '0';
138 variable iackw : slbit := '0';
139 variable iactr : slbit := '0';
140 variable iactw : slbit := '0';
141 begin
142
143 r := R_REGS;
144 n := R_REGS;
145 n.ackr := '0';
146
147 ibusy := '0';
148 iackw := '0';
149 iactr := '0';
150 iactw := '0';
151
152 case r.state is
153 when s_idle => -- s_idle: wait for req
154 n.cellen := (others=>'0');
155 n.cellwe := (others=>'0');
156 if REQ = '1' then
157 n.muxaddr := ADDR(MAWIDTH-1+12 downto 12);
158 n.celladdr := ADDR(11 downto 0);
159 n.dibuf := DI;
160 n.cellen(to_integer(unsigned(ADDR(MAWIDTH-1+12 downto 12)))) := '1';
161 if WE = '1' then
162 n.cellwe := BE;
163 n.state := s_write;
164 else
165 n.state := s_read0;
166 end if;
167 end if;
168
169 when s_read0 => -- s_read0
170 ibusy := '1';
171 iactr := '1';
172 n.state := s_read1;
173
174 when s_read1 => -- s_read1
175 ibusy := '1';
176 iactr := '1';
177 n.dobuf := MEM_DO(to_integer(unsigned(r.muxaddr)));
178 n.ackr := '1';
179 n.state := s_idle;
180
181 when s_write => -- s_write
182 ibusy := '1';
183 iactw := '1';
184 iackw := '1';
185 n.cellwe := (others=>'0');
186 n.state := s_idle;
187
188 when others => null;
189 end case;
190
191 N_REGS <= n;
192
193 BUSY <= ibusy;
194 ACK_R <= r.ackr;
195 ACK_W <= iackw;
196 ACT_R <= iactr;
197 ACT_W <= iactw;
198 DO <= r.dobuf;
199 end process proc_next;
200
201end syn;
regs_type :=( s_idle, muxaddrzero,( others => '0'), cellenzero,( others => '0'),( others => '0'),( others => '0'), '0') regs_init
slv( MAWIDTH- 1 downto 0) :=( others => '0') muxaddrzero
mem_do_type :=( others =>( others => '0')) MEM_DO
(s_idle,s_read0,s_read1,s_write) state_type
( NBLOCK- 1 downto 0) slv32 mem_do_type
regs_type := regs_init R_REGS
slv( 2** MAWIDTH- 1 downto 0) :=( others => '0') cellenzero
NBLOCK positive := 11
MAWIDTH positive := 4
Definition: pdp11.vhd:123
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31