22use ieee.std_logic_1164.
all;
23use ieee.numeric_std.
all;
94 report "assert(MAWIDTH <= 8)" severity failure;
96 report "assert(NBLOCK <= 2**MAWIDTH)" severity failure;
102 MARRAY: for row in NBLOCK-1 downto 0 generate
103 MROW: for col in 3 downto 0 generate
111 EN => R_REGS.cellen
(row
),
112 WE => R_REGS.cellwe
(col
),
113 ADDR => R_REGS.celladdr,
114 DI => R_REGS.dibuf
(8*col+7
downto 8*col
),
115 DO =>
MEM_DO(row
)(8*col+7
downto 8*col
)
123 if rising_edge(CLK) then
131 end process proc_regs;
137 variable ibusy : slbit := '0';
138 variable iackw : slbit := '0';
139 variable iactr : slbit := '0';
140 variable iactw : slbit := '0';
154 n.cellen := (others=>'0');
155 n.cellwe := (others=>'0');
158 n.celladdr := ADDR(11 downto 0);
160 n.cellen(to_integer(unsigned(ADDR(MAWIDTH-1+12 downto 12)))) := '1';
177 n.dobuf := MEM_DO(to_integer(unsigned(r.muxaddr)));
185 n.cellwe := (others=>'0');
199 end process proc_next;
regs_type :=( s_idle, muxaddrzero,( others => '0'), cellenzero,( others => '0'),( others => '0'),( others => '0'), '0') regs_init
slv( MAWIDTH- 1 downto 0) :=( others => '0') muxaddrzero
mem_do_type :=( others =>( others => '0')) MEM_DO
(s_idle,s_read0,s_read1,s_write) state_type
( NBLOCK- 1 downto 0) slv32 mem_do_type
regs_type := regs_init R_REGS
slv( 2** MAWIDTH- 1 downto 0) :=( others => '0') cellenzero
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 31 downto 0) slv32