w11 - vhd 0.794
W11 CPU core and support modules
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rlink_core8.vhd
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1-- $Id: rlink_core8.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rlink_core8 - syn
7-- Description: rlink core with 8bit interface (core+b2c/c2b+rlmon+rbmon)
8--
9-- Dependencies: rlink_core
10-- comlib/byte2cdata
11-- comlib/cdata2byte
12-- rlink_mon_sb [sim only, for 8bit level]
13--
14-- Test bench: -
15--
16-- Target Devices: generic
17-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
18--
19-- Synthesized (xst):
20-- Date Rev ise Target flop lutl lutm slic t peri
21-- 2014-12-05 596 14.7 131013 xc6slx16-2 352 492 24 176 s 7.0 ver 4.0
22-- 2011-12-09 437 13.1 O40d xc3s1000-4 184 403 0 244 s 9.1
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2015-04-11 666 4.1 add ESCXON,ESCFILL in signals, for cdata2byte
27-- 2014-10-12 596 4.0 now rlink v4 iface, 4 bit STAT
28-- 2011-12-09 437 1.0 Initial version
29------------------------------------------------------------------------------
30
31library ieee;
32use ieee.std_logic_1164.all;
33use ieee.numeric_std.all;
34
35use work.slvtypes.all;
36use work.comlib.all;
37use work.rblib.all;
38use work.rlinklib.all;
39
40entity rlink_core8 is -- rlink core with 8bit interface
41 generic (
42 BTOWIDTH : positive := 5; -- rbus timeout counter width
43 RTAWIDTH : positive := 12; -- retransmit buffer address width
44 SYSID : slv32 := (others=>'0'); -- rlink system id
45 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
46 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
47 ENAPIN_RBMON : integer := -1); -- SB_CNTL for rbmon (-1=none)
48 port (
49 CLK : in slbit; -- clock
50 CE_INT : in slbit := '0'; -- rlink ato time unit clock enable
51 RESET : in slbit; -- reset
52 ESCXON : in slbit; -- enable xon/xoff escaping
53 ESCFILL : in slbit; -- enable fill escaping
54 RLB_DI : in slv8; -- rlink 8b: data in
55 RLB_ENA : in slbit; -- rlink 8b: data enable
56 RLB_BUSY : out slbit; -- rlink 8b: data busy
57 RLB_DO : out slv8; -- rlink 8b: data out
58 RLB_VAL : out slbit; -- rlink 8b: data valid
59 RLB_HOLD : in slbit; -- rlink 8b: data hold
60 RL_MONI : out rl_moni_type; -- rlink: monitor port
61 RB_MREQ : out rb_mreq_type; -- rbus: request
62 RB_SRES : in rb_sres_type; -- rbus: response
63 RB_LAM : in slv16; -- rbus: look at me
64 RB_STAT : in slv4 -- rbus: status flags
65 );
66end entity rlink_core8;
67
68
69architecture syn of rlink_core8 is
70
71 signal RL_DI : slv9 := (others=>'0');
72 signal RL_ENA : slbit := '0';
73 signal RL_BUSY : slbit := '0';
74 signal RL_DO : slv9 := (others=>'0');
75 signal RL_VAL : slbit := '0';
76 signal RL_HOLD : slbit := '0';
77 signal RLB_BUSY_L : slbit := '0';
78 signal RLB_DO_L : slv8 := (others=>'0');
79 signal RLB_VAL_L : slbit := '0';
80
81begin
82
83 RL : rlink_core
84 generic map (
87 SYSID => SYSID,
90 port map (
91 CLK => CLK,
92 CE_INT => CE_INT,
93 RESET => RESET,
94 RL_DI => RL_DI,
95 RL_ENA => RL_ENA,
97 RL_DO => RL_DO,
98 RL_VAL => RL_VAL,
100 RL_MONI => RL_MONI,
101 RB_MREQ => RB_MREQ,
102 RB_SRES => RB_SRES,
103 RB_LAM => RB_LAM,
105 );
106
107-- RLB -> RL converter (DI handling) -------------
108 B2CD : byte2cdata -- byte stream -> 9bit comma,data
109 port map (
110 CLK => CLK,
111 RESET => RESET,
112 DI => RLB_DI,
113 ENA => RLB_ENA,
114 ERR => '0',
115 BUSY => RLB_BUSY_L,
116 DO => RL_DI,
117 VAL => RL_ENA,
118 HOLD => RL_BUSY
119 );
120
121-- RL -> RLB converter (DO handling) -------------
122 CD2B : cdata2byte -- 9bit comma,data -> byte stream
123 port map (
124 CLK => CLK,
125 RESET => RESET,
126 ESCXON => ESCXON,
127 ESCFILL => ESCFILL,
128 DI => RL_DO,
129 ENA => RL_VAL,
130 BUSY => RL_HOLD,
131 DO => RLB_DO_L,
132 VAL => RLB_VAL_L,
133 HOLD => RLB_HOLD
134 );
135
137 RLB_DO <= RLB_DO_L;
139
140-- synthesis translate_off
141
142 RLBMON: if ENAPIN_RLBMON >= 0 generate
143 MON : rlink_mon_sb
144 generic map (
145 DWIDTH => RLB_DI'length,
147 port map (
148 CLK => CLK,
149 RL_DI => RLB_DI,
150 RL_ENA => RLB_ENA,
152 RL_DO => RLB_DO_L,
153 RL_VAL => RLB_VAL_L,
155 );
156 end generate RLBMON;
157
158-- synthesis translate_on
159
160end syn;
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 8 downto 0) slv9
Definition: slvtypes.vhd:41
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40