w11 - vhd 0.794
W11 CPU core and support modules
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sramif_mig_arty.vhd
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1-- $Id: sramif_mig_arty.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sramif_mig_arty - syn
7-- Description: SRAM to DDR via MIG for arty
8--
9-- Dependencies: bplib/mig/sramif2migui_core
10-- cdclib/cdc_pulse
11-- cdclib/cdc_value
12-- migui_arty (generated core)
13-- Test bench: tb_tst_sram_arty
14-- Target Devices: arty board
15-- Tool versions: viv 2017.2; ghdl 0.34
16--
17-- Revision History:
18-- Date Rev Version Comment
19-- 2019-01-02 1101 1.0 Initial version
20-- 2018-11-17 1071 0.1 First draft
21--
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26use ieee.numeric_std.all;
27
28use work.slvtypes.all;
29use work.cdclib.all;
30use work.miglib.all;
31use work.miglib_arty.all;
32
33entity sramif_mig_arty is -- SRAM to DDR via MIG for arty
34 port (
35 CLK : in slbit; -- clock
36 RESET : in slbit; -- reset
37 REQ : in slbit; -- request
38 WE : in slbit; -- write enable
39 BUSY : out slbit; -- controller busy
40 ACK_R : out slbit; -- acknowledge read
41 ACK_W : out slbit; -- acknowledge write
42 ACT_R : out slbit; -- signal active read
43 ACT_W : out slbit; -- signal active write
44 ADDR : in slv20; -- address (32 bit word address)
45 BE : in slv4; -- byte enable
46 DI : in slv32; -- data in (memory view)
47 DO : out slv32; -- data out (memory view)
48 CLKMIG : in slbit; -- sys clock for mig core
49 CLKREF : in slbit; -- ref clock for mig core
50 TEMP : in slv12; -- xadc die temp for mig core
51 MONI : out sramif2migui_moni_type;-- monitor signals
52 DDR3_DQ : inout slv16; -- dram: data in/out
53 DDR3_DQS_P : inout slv2; -- dram: data strobe (diff-p)
54 DDR3_DQS_N : inout slv2; -- dram: data strobe (diff-n)
55 DDR3_ADDR : out slv14; -- dram: address
56 DDR3_BA : out slv3; -- dram: bank address
57 DDR3_RAS_N : out slbit; -- dram: row addr strobe (act.low)
58 DDR3_CAS_N : out slbit; -- dram: column addr strobe (act.low)
59 DDR3_WE_N : out slbit; -- dram: write enable (act.low)
60 DDR3_RESET_N : out slbit; -- dram: reset (act.low)
61 DDR3_CK_P : out slv1; -- dram: clock (diff-p)
62 DDR3_CK_N : out slv1; -- dram: clock (diff-n)
63 DDR3_CKE : out slv1; -- dram: clock enable
64 DDR3_CS_N : out slv1; -- dram: chip select (act.low)
65 DDR3_DM : out slv2; -- dram: data input mask
66 DDR3_ODT : out slv1 -- dram: on-die termination
67 );
69
70
71architecture syn of sramif_mig_arty is
72
73 signal MIG_BUSY : slbit := '0';
74
75 signal APP_RDY : slbit := '0';
76 signal APP_EN : slbit := '0';
77 signal APP_CMD : slv3 := (others=>'0');
78 signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
79 signal APP_WDF_RDY : slbit := '0';
80 signal APP_WDF_WREN : slbit := '0';
81 signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
82 signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
83 signal APP_WDF_END : slbit := '0';
84 signal APP_RD_DATA_VALID : slbit := '0';
85 signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
86 signal APP_RD_DATA_END : slbit := '0';
87
88 signal UI_CLK_SYNC_RST : slbit := '0';
89 signal INIT_CALIB_COMPLETE : slbit := '0';
90
91 signal SYS_RST : slbit := '0';
92 signal SYS_RST_BUSY : slbit := '0';
93
94 signal CLKMUI : slbit := '0';
95 signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
96
97begin
98
99 SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
100 generic map (
101 BAWIDTH => mig_bawidth,
102 MAWIDTH => mig_mawidth)
103 port map (
104 CLK => CLK,
105 RESET => RESET,
106 REQ => REQ,
107 WE => WE,
108 BUSY => MIG_BUSY,
109 ACK_R => ACK_R,
110 ACK_W => ACK_W,
111 ACT_R => ACT_R,
112 ACT_W => ACT_W,
113 ADDR => ADDR,
114 BE => BE,
115 DI => DI,
116 DO => DO,
117 MONI => MONI,
118 UI_CLK => CLKMUI,
119 UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
120 INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
121 APP_RDY => APP_RDY,
122 APP_EN => APP_EN,
123 APP_CMD => APP_CMD,
124 APP_ADDR => APP_ADDR,
125 APP_WDF_RDY => APP_WDF_RDY,
126 APP_WDF_WREN => APP_WDF_WREN,
127 APP_WDF_DATA => APP_WDF_DATA,
128 APP_WDF_MASK => APP_WDF_MASK,
129 APP_WDF_END => APP_WDF_END,
130 APP_RD_DATA_VALID => APP_RD_DATA_VALID,
131 APP_RD_DATA => APP_RD_DATA,
132 APP_RD_DATA_END => APP_RD_DATA_END
133 );
134
135 CDC_SYSRST: cdc_pulse
136 generic map (
137 POUT_SINGLE => false,
138 BUSY_WACK => true)
139 port map (
140 CLKM => CLK,
141 RESET => '0',
142 CLKS => CLKMIG,
143 PIN => RESET,
145 POUT => SYS_RST
146 );
147
148 CDC_TEMP: cdc_value
149 generic map (
150 DWIDTH => TEMP'length)
151 port map (
152 CLKI => CLK,
153 CLKO => CLKMUI,
154 DI => TEMP,
155 DO => TEMP_MUI,
156 UPDT => open
157 );
158
159 MIG_CTL: migui_arty
160 port map (
161 DDR3_DQ => DDR3_DQ,
165 DDR3_BA => DDR3_BA,
174 DDR3_DM => DDR3_DM,
177 APP_CMD => APP_CMD,
178 APP_EN => APP_EN,
186 APP_RDY => APP_RDY,
188 APP_SR_REQ => '0',
189 APP_REF_REQ => '0',
190 APP_ZQ_REQ => '0',
191 APP_SR_ACTIVE => open,
192 APP_REF_ACK => open,
193 APP_ZQ_ACK => open,
194 UI_CLK => CLKMUI,
197 SYS_CLK_I => CLKMIG,
198 CLK_REF_I => CLKREF,
201 );
202
204
205end syn;
in CLKM slbit
Definition: cdc_pulse.vhd:32
out BUSY slbit
Definition: cdc_pulse.vhd:36
out POUT slbit
Definition: cdc_pulse.vhd:38
in CLKS slbit
Definition: cdc_pulse.vhd:34
in PIN slbit
Definition: cdc_pulse.vhd:35
BUSY_WACK boolean := false
Definition: cdc_pulse.vhd:29
in RESET slbit := '0'
Definition: cdc_pulse.vhd:33
POUT_SINGLE boolean := false
Definition: cdc_pulse.vhd:28
out DO slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:34
in CLKO slbit
Definition: cdc_value.vhd:32
in DI slv( DWIDTH- 1 downto 0)
Definition: cdc_value.vhd:33
in CLKI slbit
Definition: cdc_value.vhd:31
out UPDT slbit
Definition: cdc_value.vhd:36
DWIDTH positive := 16
Definition: cdc_value.vhd:29
out UI_CLK slbit
out DDR3_CK_P slv1
out APP_RD_DATA slv( mig_dwidth- 1 downto 0)
out APP_RDY slbit
out APP_RD_DATA_VALID slbit
out DDR3_DM slv2
out APP_REF_ACK slbit
out APP_RD_DATA_END slbit
out DDR3_RESET_N slbit
out DDR3_BA slv3
inout DDR3_DQ slv16
in APP_WDF_MASK slv( mig_mwidth- 1 downto 0)
in APP_WDF_END slbit
in DEVICE_TEMP_I slv12
out INIT_CALIB_COMPLETE slbit
in APP_SR_REQ slbit
out DDR3_WE_N slbit
out DDR3_CKE slv1
out DDR3_ADDR slv14
out DDR3_ODT slv1
out DDR3_CAS_N slbit
out DDR3_CK_N slv1
inout DDR3_DQS_P slv2
in APP_REF_REQ slbit
in SYS_RST slbit
out APP_ZQ_ACK slbit
out APP_WDF_RDY slbit
inout DDR3_DQS_N slv2
in APP_ZQ_REQ slbit
in CLK_REF_I slbit
in APP_WDF_WREN slbit
out APP_SR_ACTIVE slbit
in APP_EN slbit
in APP_CMD slv3
in APP_ADDR slv( mig_mawidth- 1 downto 0)
in SYS_CLK_I slbit
out DDR3_RAS_N slbit
out DDR3_CS_N slv1
in APP_WDF_DATA slv( mig_dwidth- 1 downto 0)
out UI_CLK_SYNC_RST slbit
std_logic_vector( 13 downto 0) slv14
Definition: slvtypes.vhd:46
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' APP_RD_DATA_VALID
slbit := '0' APP_RD_DATA_END
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_RD_DATA
slv( mig_mawidth- 1 downto 0) :=( others => '0') APP_ADDR
slbit := '0' UI_CLK_SYNC_RST
slv3 :=( others => '0') APP_CMD
slv( mig_mwidth- 1 downto 0) :=( others => '0') APP_WDF_MASK
slbit := '0' APP_WDF_END
slbit := '0' APP_WDF_RDY
slbit := '0' APP_WDF_WREN
slbit := '0' INIT_CALIB_COMPLETE
slbit := '0' SYS_RST_BUSY
slv( mig_dwidth- 1 downto 0) :=( others => '0') APP_WDF_DATA
slv12 :=( others => '0') TEMP_MUI
out DDR3_RESET_N slbit
inout DDR3_DQ slv16
out DDR3_WE_N slbit
out DDR3_ADDR slv14
out DDR3_CAS_N slbit
inout DDR3_DQS_P slv2
out MONI sramif2migui_moni_type
inout DDR3_DQS_N slv2
out DDR3_RAS_N slbit