w11 - vhd 0.794
W11 CPU core and support modules
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tb_pdp11core.vhd
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1-- $Id: tb_pdp11core.vhd 1310 2022-10-27 16:15:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_pdp11core - sim
7-- Description: Test bench for pdp11_core
8--
9-- Dependencies: simlib/simclk
10-- tbd_pdp11core [UUT]
11-- pdp11_intmap
12--
13-- To test: pdp11_core
14--
15-- Target Devices: generic
16-- Tool versions: ghdl 0.18-2.0.0; ISim 14.7
17--
18-- Verified (with tb_pdp11core_stim.dat):
19-- Date Rev Code ghdl ise Target Comment
20-- 2014-12-23 620 - 0.31 14.7 131013 - u:ok
21-- 2010-12-30 351 - 0.29 - - u:ok
22-- 2010-12-30 351 _ssim 0.29 12.1 M53d xc3s1000 u:ok
23-- 2010-06-20 308 - 0.29 - - u:ok
24-- 2009-11-22 252 - 0.26 - - u:ok
25-- 2007-12-30 107 - 0.25 - - u:ok
26-- 2007-10-26 92 _tsim 0.26 8.1.03 I27 xc3s1000 c:fail -> blog_ghdl
27-- 2007-10-26 92 _tsim 0.26 9.2.02 J39 xc3s1000 d:ok (full tsim!)
28-- 2007-10-26 92 _tsim 0.26 9.1 J30 xc3s1000 d:ok (full tsim!)
29-- 2007-10-26 92 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok (full tsim!)
30-- 2007-10-26 92 _fsim 0.26 8.2.03 I34 xc3s1000 d:ok
31-- 2007-10-26 92 _ssim 0.26 8.2.03 I34 xc3s1000 d:ok
32-- 2007-10-08 88 _ssim 0.18 8.2.03 I34 xc3s1000 d:ok
33-- 2007-10-08 88 _ssim 0.18 9.1 J30 xc3s1000 d:ok
34-- 2007-10-08 88 _ssim 0.18 9.2.02 J39 xc3s1000 d:ok
35-- 2007-10-07 88 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
36-- 2007-10-07 88 _ssim 0.26 8.1 I24 xc3s1000 c:fail -> blog_webpack
37-- 2007-10-07 88 - 0.26 - - c:ok
38--
39-- Revision History:
40-- Date Rev Version Comment
41-- 2022-10-25 1309 1.5.2 rename _gpr -> _gr
42-- 2019-03-17 1123 1.5.1 print header
43-- 2015-05-08 675 1.5 start/stop/suspend overhaul
44-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
45-- 2011-12-23 444 1.4 use new simclk/simclkcnt
46-- 2011-11-18 427 1.3.2 now numeric_std clean
47-- 2011-01-02 352 1.3.1 rename .cpmon->.rlmon
48-- 2010-12-30 351 1.3 rename tb_pdp11_core -> tb_pdp11core
49-- 2010-06-20 308 1.2.2 add wibrb, ribr, wibr commands for ibr accesses
50-- 2010-06-20 307 1.2.1 add CP_ADDR_racc, CP_ADDR_be to tbd interface
51-- 2010-06-13 305 1.2 add CP_CNTL_rnum and CP_ADDR_...; emulate old
52-- 'sta' behaviour with new 'stapc' command; rename
53-- lal,lah -> wal,wah and implement locally; new
54-- output format with cpfunc name
55-- 2010-06-05 301 1.1.14 renamed .rpmon -> .rbmon
56-- 2010-04-24 281 1.1.13 use direct instatiation for tbd_
57-- 2009-11-28 253 1.1.12 add hack for ISim 11.3
58-- 2009-05-10 214 1.1.11 add .scntl command (set/clear SB_CNTL bits)
59-- 2008-08-29 163 1.1.10 allow, but ignore, the wtlam command
60-- 2008-05-03 143 1.1.9 rename _cpursta->_cpurust
61-- 2008-04-27 140 1.1.8 use cpursta interface, remove cpufail
62-- 2008-04-19 137 1.1.7 use SB_CLKCYCLE now
63-- 2008-03-24 129 1.1.6 CLK_CYCLE now 31 bits
64-- 2008-03-02 121 1.1.5 redo sta,cont,wtgo commands; sta,cont now wait for
65-- command completion, wtgo waits for CPU to halt.
66-- added .cerr,.merr directive, check cmd(m)err state
67-- added .sdef as ignored directive
68-- 2008-02-24 119 1.1.4 added lah,rps,wps command
69-- 2008-01-26 114 1.1.3 add handling of d=val,msk
70-- 2008-01-06 111 1.1.2 remove .eireq, EI's now handled in tbd_pdp11_core
71-- 2007-10-26 92 1.0.2 use DONE timestamp at end of execution
72-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
73-- 2007-09-02 79 1.0 Initial version
74------------------------------------------------------------------------------
75
76library ieee;
77use ieee.std_logic_1164.all;
78use ieee.numeric_std.all;
79use ieee.std_logic_textio.all;
80use std.textio.all;
81
82use work.slvtypes.all;
83use work.simlib.all;
84use work.simbus.all;
85use work.pdp11_sim.all;
86use work.pdp11.all;
87
88entity tb_pdp11core is
89end tb_pdp11core;
90
91architecture sim of tb_pdp11core is
92
93 signal CLK : slbit := '0';
94 signal RESET : slbit := '0';
95 signal UNUSEDSIGNAL : slbit := '0'; -- FIXME: hack to make ISim 11.3 happy
96 signal CP_CNTL_req : slbit := '0';
97 signal CP_CNTL_func : slv5 := (others=>'0');
98 signal CP_CNTL_rnum : slv3 := (others=>'0');
99 signal CP_ADDR_addr : slv22_1 := (others=>'0');
100 signal CP_ADDR_racc : slbit := '0';
101 signal CP_ADDR_be : slv2 := "11";
102 signal CP_ADDR_ena_22bit : slbit := '0';
103 signal CP_ADDR_ena_ubmap : slbit := '0';
104 signal CP_DIN : slv16 := (others=>'0');
105 signal CP_STAT_cmdbusy : slbit := '0';
106 signal CP_STAT_cmdack : slbit := '0';
107 signal CP_STAT_cmderr : slbit := '0';
108 signal CP_STAT_cmdmerr : slbit := '0';
109 signal CP_STAT_cpugo : slbit := '0';
110 signal CP_STAT_cpustep : slbit := '0';
111 signal CP_STAT_cpuwait : slbit := '0';
112 signal CP_STAT_cpususp : slbit := '0';
113 signal CP_STAT_cpurust : slv4 := (others=>'0');
114 signal CP_STAT_suspint : slbit := '0';
115 signal CP_STAT_suspext : slbit := '0';
116 signal CP_DOUT : slv16 := (others=>'0');
117
118 signal CLK_STOP : slbit := '0';
119 signal CLK_CYCLE : integer := 0;
120
121 signal R_CHKDAT : slv16 := (others=>'0');
122 signal R_CHKMSK : slv16 := (others=>'0');
123 signal R_CHKREQ : slbit := '0';
124
125 signal R_WAITCMD : slbit := '0';
126 signal R_WAITSTEP : slbit := '0';
127 signal R_WAITGO : slbit := '0';
128 signal R_WAITOK : slbit := '0';
129 signal R_CP_STAT : cp_stat_type := cp_stat_init;
130 signal R_CP_DOUT : slv16 := (others=>'0');
131
132begin
133
134 CLKGEN : simclk
135 generic map (
136 PERIOD => clock_period,
137 OFFSET => clock_offset)
138 port map (
139 CLK => CLK,
140 CLK_STOP => CLK_STOP
141 );
142
143 CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
144
145 UUT: entity work.tbd_pdp11core
146 port map (
147 CLK => CLK,
148 RESET => RESET,
149 CP_CNTL_req => CP_CNTL_req,
150 CP_CNTL_func => CP_CNTL_func,
151 CP_CNTL_rnum => CP_CNTL_rnum,
152 CP_ADDR_addr => CP_ADDR_addr,
153 CP_ADDR_racc => CP_ADDR_racc,
154 CP_ADDR_be => CP_ADDR_be,
155 CP_ADDR_ena_22bit => CP_ADDR_ena_22bit,
156 CP_ADDR_ena_ubmap => CP_ADDR_ena_ubmap,
157 CP_DIN => CP_DIN,
158 CP_STAT_cmdbusy => CP_STAT_cmdbusy,
159 CP_STAT_cmdack => CP_STAT_cmdack,
160 CP_STAT_cmderr => CP_STAT_cmderr,
161 CP_STAT_cmdmerr => CP_STAT_cmdmerr,
162 CP_STAT_cpugo => CP_STAT_cpugo,
163 CP_STAT_cpustep => CP_STAT_cpustep,
164 CP_STAT_cpuwait => CP_STAT_cpuwait,
165 CP_STAT_cpususp => CP_STAT_cpususp,
166 CP_STAT_cpurust => CP_STAT_cpurust,
167 CP_STAT_suspint => CP_STAT_suspint,
168 CP_STAT_suspext => CP_STAT_suspext,
169 CP_DOUT => CP_DOUT
170 );
171
172 proc_stim: process
173 file ifile : text open read_mode is "tb_pdp11core_stim";
174 variable iline : line;
175 variable oline : line;
176 variable idelta : integer := 0;
177 variable idummy : integer := 0;
178 variable dcycle : integer := 0;
179 variable irqline : integer := 0;
180 variable ireq : boolean := false;
181 variable ifunc : slv5 := (others=>'0');
182 variable irnum : slv3 := (others=>'0');
183 variable idin : slv16 := (others=>'0');
184 variable imsk : slv16 := (others=>'1');
185 variable idin3 : slv3 := (others=>'0');
186 variable ichk : boolean := false;
187 variable idosta: slbit := '0';
188
189 variable ok : boolean;
190 variable dname : string(1 to 6) := (others=>' ');
191 variable rind : integer := 0;
192 variable nblk : integer := 0;
193 variable xmicmd : string(1 to 3) := (others=>' ');
194 variable iwtstp : boolean := false;
195 variable iwtgo : boolean := false;
196 variable icerr : integer := 0;
197 variable imerr : integer := 0;
198 variable to_cmd : integer := 50;
199 variable to_stp : integer := 100;
200 variable to_go : integer := 5000;
201 variable ien : slbit := '0';
202 variable ibit : integer := 0;
203 variable imemi : boolean := false;
204 variable iaddr : slv16 := (others=>'0');
205 variable idoibr : boolean := false;
206
207 variable r_addr : slv22_1 := (others=>'0');
208 variable r_ena_22bit : slbit := '0';
209 variable r_ena_ubmap : slbit := '0';
210 variable r_membe : slv2 := "11";
211 variable r_membestick : slbit := '0';
212
213 begin
214
215 SB_CNTL <= (others=>'L');
216
217 wait for clock_offset - setup_time;
218
219 RESET <= '1';
220 wait for clock_period;
221
222 RESET <= '0';
223 wait for 9*clock_period;
224
225 -- write header
226 write(oline, string'(" # cycles"));
227 writeline(output, oline);
228 write(oline, string'(" | function"));
229 writeline(output, oline);
230 write(oline, string'(" | | register"));
231 writeline(output, oline);
232 write(oline, string'(" | | | input data"));
233 writeline(output, oline);
234 write(oline, string'(" | | | | cmdbusy"));
235 writeline(output, oline);
236 write(oline, string'(" | | | | | cmdack"));
237 writeline(output, oline);
238 write(oline, string'(" | | | | | | cmderr"));
239 writeline(output, oline);
240 write(oline, string'(" | | | | | | | cmdmerr"));
241 writeline(output, oline);
242 write(oline, string'(" | | | | | | | | output data"));
243 writeline(output, oline);
244 write(oline, string'(" | | | | | | | | | cpugo"));
245 writeline(output, oline);
246 write(oline, string'(" | | | | | | | | | |cpustep"));
247 writeline(output, oline);
248 write(oline, string'(" | | | | | | | | | ||cpuwait"));
249 writeline(output, oline);
250 write(oline, string'(" | | | | | | | | | |||cpususp"));
251 writeline(output, oline);
252 write(oline, string'(" | | | | | | | | | ||||suspint"));
253 writeline(output, oline);
254 write(oline, string'(" | | | | | | | | | |||||suspext"));
255 writeline(output, oline);
256 write(oline,
257 string'(" | | | | | | | | | |||||| cpurust"));
258 writeline(output, oline);
259 write(oline,
260 string'(" | | | | | | | | | |||||| | Check result"));
261 writeline(output, oline);
262 write(oline,
263 string'(" | | | | | | | | | |||||| | |"));
264 writeline(output, oline);
265
266 file_loop: while not endfile(ifile) loop
267
268 -- this logic is a quick hack to implement the 'stapc' command
269 if idosta = '0' then
270 readline (ifile, iline);
271
272 iwtstp := false;
273 iwtgo := false;
274
275 if nblk>0 and -- outstanding [rw]mi lines ?
276 iline'length>=3 and -- and 3 leading blanks
277 iline(iline'left to iline'left+2)=" " then
278 nblk := nblk - 1; -- than fill [rw]mi command in again
279 iline(iline'left to iline'left+2) := xmicmd;
280 end if;
281
282 readcomment(iline, ok);
283 next file_loop when ok;
284
285 readword(iline, dname, ok);
286
287 else
288 idosta := '0';
289 dname := "sta ";
290 ok := true;
291 end if;
292
293 if ok then
294
295 case dname is
296 when "rsp " => dname := "rr6 "; -- rsp -> rr6
297 when "rpc " => dname := "rr7 "; -- rpc -> rr7
298 when "wsp " => dname := "wr6 "; -- wsp -> wr6
299 when "wpc " => dname := "wr7 "; -- wpc -> wr7
300 when others => null;
301 end case;
302
303 rind := character'pos(dname(3)) - character'pos('0');
304
305 if (dname(1)='r' or dname(1)='w') and -- check for [rw]r[0-7]
306 dname(2)='r' and
307 (rind>=0 and rind<=7) then
308 dname(3) := '|'; -- replace with [rw]r|
309 end if;
310
311 if dname(1) = '.' then
312 case dname is
313 when ".mode " => -- .mode
314 readword_ea(iline, dname);
315 assert dname="pdpcp "
316 report "assert .mode == pdpcp" severity failure;
317
318 when ".reset" => -- .reset
319 write(oline, string'(".reset"));
320 writeline(output, oline);
321 RESET <= '1';
322 wait for clock_period;
323
324 RESET <= '0';
325 wait for 9*clock_period;
326
327 when ".wait " => -- .wait
328 read_ea(iline, idelta);
329 wait for idelta*clock_period;
330
331 when ".tocmd" => -- .tocmd
332 read_ea(iline, idelta);
333 to_cmd := idelta;
334
335 when ".tostp" => -- .tostp
336 read_ea(iline, idelta);
337 to_stp := idelta;
338
339 when ".togo " => -- .togo
340 read_ea(iline, idelta);
341 to_go := idelta;
342
343 when ".sdef " => -- .sdef (ignore it)
344 readempty(iline);
345
346 when ".cerr " => -- .cerr
347 read_ea(iline, icerr);
348 when ".merr " => -- .merr
349 read_ea(iline, imerr);
350
351 when ".anena" => -- .anena (ignore it)
352 readempty(iline);
353 when ".rlmon" => -- .rlmon (ignore it)
354 readempty(iline);
355 when ".rbmon" => -- .rbmon (ignore it)
356 readempty(iline);
357
358 when ".scntl" => -- .scntl
359 read_ea(iline, ibit);
360 read_ea(iline, ien);
361 assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
362 report "assert bit number in range of SB_CNTL"
363 severity failure;
364 if ien = '1' then
365 SB_CNTL(ibit) <= 'H';
366 else
367 SB_CNTL(ibit) <= 'L';
368 end if;
369
370 when others => -- bad directive
371 write(oline, string'("-E: unknown directive: "));
372 write(oline, dname);
373 writeline(output, oline);
374 report "aborting" severity failure;
375 end case;
376
377 testempty_ea(iline);
378 next file_loop;
379
380 else
381
382 ireq := true;
383 ifunc := c_cpfunc_noop;
384 irnum := "000";
385 ichk := false;
386 idin := (others=>'0');
387 imsk := (others=>'1');
388 imemi := false;
389 idoibr := false;
390
391 case dname is
392 when "brm " => -- brm
393 read_ea(iline, nblk);
394 xmicmd := "rmi";
395 next file_loop;
396 when "bwm " => -- bwm
397 read_ea(iline, nblk);
398 xmicmd := "wmi";
399 next file_loop;
400
401 when "rr| " => -- rr[0-7]
402 ifunc := c_cpfunc_rreg;
403 irnum := slv(to_unsigned(rind, 3));
404 readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
405
406 when "wr| " => -- wr[0-7]
407 ifunc := c_cpfunc_wreg;
408 irnum := slv(to_unsigned(rind, 3));
409 readoct_ea(iline, idin);
410
411 -- Note: there are no field definitions for wal, wah, wmembe because
412 -- there is no corresponding cp command. Therefore the
413 -- rbus field definitions are used here
414 when "wal " => -- wal
415 readoct_ea(iline, idin);
416 r_addr := (others=>'0'); -- write to al clears ah !!
417 r_ena_22bit := '0';
418 r_ena_ubmap := '0';
419 r_addr(c_al_rbf_addr) := idin(c_al_rbf_addr);
420 testempty_ea(iline);
421 next file_loop;
422
423 when "wah " => -- wah
424 readoct_ea(iline, idin);
425 r_addr(21 downto 16) := idin(c_ah_rbf_addr);
426 r_ena_22bit := idin(c_ah_rbf_ena_22bit);
427 r_ena_ubmap := idin(c_ah_rbf_ena_ubmap);
428 testempty_ea(iline);
429 next file_loop;
430
431 when "wmembe" => -- wmembe
432 read_ea(iline, idin3);
433 r_membestick := idin3(c_membe_rbf_stick);
434 r_membe := idin3(c_membe_rbf_be);
435 testempty_ea(iline);
436 next file_loop;
437
438 when "rm " => -- rm
439 ifunc := c_cpfunc_rmem;
440 readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
441 when "rmi " => -- rmi
442 ifunc := c_cpfunc_rmem;
443 imemi := true;
444 readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
445
446 when "wm " => -- wm
447 ifunc := c_cpfunc_wmem;
448 readoct_ea(iline, idin);
449 when "wmi " => -- wmi
450 ifunc := c_cpfunc_wmem;
451 imemi := true;
452 readoct_ea(iline, idin);
453
454 when "ribr " => -- ribr
455 ifunc := c_cpfunc_rmem;
456 idoibr := true;
457 readoct_ea(iline, iaddr);
458 readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
459 when "wibr " => -- wibr
460 ifunc := c_cpfunc_wmem;
461 idoibr := true;
462 readoct_ea(iline, iaddr);
463 readoct_ea(iline, idin);
464
465 when "rps " => -- rps
466 ifunc := c_cpfunc_rpsw;
467 readtagval2_ea(iline, "d", ichk, idin, imsk, 8);
468 when "wps " => -- wps
469 ifunc := c_cpfunc_wpsw;
470 readoct_ea(iline, idin);
471
472 -- Note: in old version 'sta addr' was an atomic operation, loading
473 -- the pc and starting the cpu. Now this is action is two step
474 -- first a wpc followed by a 'sta'.
475 when "stapc " => -- stapc
476 ifunc := c_cpfunc_wreg;
477 irnum := c_gr_pc;
478 readoct_ea(iline, idin);
479 idosta := '1'; -- request 'sta' to be done next
480
481 when "sta " => -- sta
482 ifunc := c_cpfunc_start;
483 when "sto " => -- sto
484 ifunc := c_cpfunc_stop;
485 when "step " => -- step
486 ifunc := c_cpfunc_step;
487 iwtstp := true;
488 when "cres " => -- cres
489 ifunc := c_cpfunc_creset;
490 when "bres " => -- bres
491 ifunc := c_cpfunc_breset;
492 when "susp " => -- susp
493 ifunc := c_cpfunc_suspend;
494 when "resu " => -- resu
495 ifunc := c_cpfunc_resume;
496
497 when "wtgo " => -- wtgo
498 iwtgo := true;
499 ireq := false; -- no cp request !
500
501 when "wtlam " => -- wtlam (ignore it)
502 readempty(iline);
503 next file_loop;
504
505 when others => -- bad directive
506 write(oline, string'("-E: unknown directive: "));
507 write(oline, dname);
508 writeline(output, oline);
509 report "aborting" severity failure;
510 end case;
511
512 end if;
513 testempty_ea(iline);
514
515 end if;
516
517 CP_ADDR_be <= r_membe;
518 if idoibr then
519 CP_ADDR_addr(15 downto 13) <= "111";
520 CP_ADDR_addr(12 downto 1) <= iaddr(12 downto 1);
521 CP_ADDR_racc <= '1';
522 CP_ADDR_ena_22bit <= '0';
523 CP_ADDR_ena_ubmap <= '0';
524 else
525 CP_ADDR_addr <= r_addr;
526 CP_ADDR_racc <= '0';
527 CP_ADDR_be <= "11";
528 CP_ADDR_ena_22bit <= r_ena_22bit;
529 CP_ADDR_ena_ubmap <= r_ena_ubmap;
530 end if;
531
532 if ireq then
533 CP_CNTL_req <= '1';
534 CP_CNTL_func <= ifunc;
535 CP_CNTL_rnum <= irnum;
536 end if;
537
538 if ichk then
539 CP_DIN <= (others=>'0');
540 R_CHKDAT <= idin;
541 R_CHKMSK <= imsk;
542 R_CHKREQ <= '1';
543 else
544 CP_DIN <= idin;
545 R_CHKREQ <= '0';
546 end if;
547
548 R_WAITCMD <= '0';
549 R_WAITSTEP <= '0';
550 R_WAITGO <= '0';
551 if iwtgo then
552 idelta := to_go;
553 R_WAITGO <= '1';
554 elsif iwtstp then
555 idelta := to_stp;
556 R_WAITSTEP <= '1';
557 else
558 idelta := to_cmd;
559 R_WAITCMD <= '1';
560 end if;
561
562 wait for clock_period;
563 CP_CNTL_req <= '0';
564
565 dcycle := 1;
566 while idelta>0 and R_WAITOK='0' loop
567 wait for clock_period;
568 dcycle := dcycle + 1;
569 idelta := idelta - 1;
570 end loop;
571
572 if imemi then -- rmi or wmi seen ? then inc ar
573 r_addr := slv(unsigned(r_addr) + 1);
574 end if;
575
576 if ifunc = c_cpfunc_wmem and -- emulate be sticky logic of rbus iface
577 r_membestick = '0' then
578 r_membe := "11";
579 end if;
580
581 write(oline, dcycle, right, 4);
582 write(oline, string'(" "));
583 if ireq then
584 case ifunc is
585 when c_cpfunc_rreg => write(oline, string'("rreg"));
586 when c_cpfunc_wreg => write(oline, string'("wreg"));
587 when c_cpfunc_rpsw => write(oline, string'("rpsw"));
588 when c_cpfunc_wpsw => write(oline, string'("wpsw"));
589 when c_cpfunc_rmem =>
590 if idoibr then
591 write(oline, string'("ribr"));
592 else
593 write(oline, string'("rmem"));
594 end if;
595 when c_cpfunc_wmem =>
596 if idoibr then
597 write(oline, string'("wibr"));
598 else
599 write(oline, string'("wmem"));
600 end if;
601 when c_cpfunc_start => write(oline, string'("sta "));
602 when c_cpfunc_stop => write(oline, string'("sto "));
603 when c_cpfunc_step => write(oline, string'("step"));
604 when c_cpfunc_creset => write(oline, string'("cres"));
605 when c_cpfunc_breset => write(oline, string'("bres"));
606 when c_cpfunc_suspend => write(oline, string'("susp"));
607 when c_cpfunc_resume => write(oline, string'("resu"));
608 when others =>
609 write(oline, string'("?"));
610 writeoct(oline, ifunc, right, 2);
611 write(oline, string'("?"));
612 end case;
613 writeoct(oline, irnum, right, 2);
614 writeoct(oline, idin, right, 8);
615 else
616 write(oline, string'("---- - ------"));
617 end if;
618
619 write(oline, R_CP_STAT.cmdbusy, right, 3);
620 write(oline, R_CP_STAT.cmdack, right, 2);
621 write(oline, R_CP_STAT.cmderr, right, 2);
622 write(oline, R_CP_STAT.cmdmerr, right, 2);
623 writeoct(oline, R_CP_DOUT, right, 8);
624 write(oline, R_CP_STAT.cpugo, right, 3);
625 write(oline, R_CP_STAT.cpustep, right, 1);
626 write(oline, R_CP_STAT.cpuwait, right, 1);
627 write(oline, R_CP_STAT.cpususp, right, 1);
628 write(oline, R_CP_STAT.suspint, right, 1);
629 write(oline, R_CP_STAT.suspext, right, 1);
630 writeoct(oline, R_CP_STAT.cpurust, right, 3);
631
632 if R_WAITOK = '1' then
633 if R_CP_STAT.cmderr='1' or icerr=1 then
634 if R_CP_STAT.cmderr='1' and icerr=0 then
635 write(oline, string'(" FAIL CMDERR"));
636 elsif R_CP_STAT.cmderr='1' and icerr=1 then
637 write(oline, string'(" CHECK CMDERR SEEN"));
638 elsif R_CP_STAT.cmderr='0' and icerr=1 then
639 write(oline, string'(" FAIL CMDERR EXPECTED,MISSED"));
640 end if;
641 elsif R_CP_STAT.cmdmerr='1' or imerr=1 then
642 if R_CP_STAT.cmdmerr='1' and imerr=0 then
643 write(oline, string'(" FAIL CMDMERR"));
644 elsif R_CP_STAT.cmdmerr='1' and imerr=1 then
645 write(oline, string'(" CHECK CMDMERR SEEN"));
646 elsif R_CP_STAT.cmdmerr='0' and imerr=1 then
647 write(oline, string'(" FAIL CMDMERR EXPECTED,MISSED"));
648 end if;
649 elsif R_CHKREQ='1' then
650 if unsigned((R_CP_DOUT xor R_CHKDAT) and (not R_CHKMSK))=0 then
651 write(oline, string'(" CHECK OK"));
652 else
653 write(oline, string'(" CHECK FAILED, d="));
654 writeoct(oline, R_CHKDAT, right, 7);
655 if unsigned(R_CHKMSK)/=0 then
656 write(oline, string'(","));
657 writeoct(oline, R_CHKMSK, right, 7);
658 end if;
659 end if;
660 end if;
661
662 if iwtgo then
663 write(oline, string'(" WAIT GO OK "));
664 elsif iwtstp then
665 write(oline, string'(" WAIT STEP OK"));
666 end if;
667
668 else
669 write(oline, string'(" WAIT FAILED (will reset)"));
670 RESET <= '1';
671 wait for clock_period;
672
673 RESET <= '0';
674 wait for 9*clock_period;
675
676 end if;
677 writeline(output, oline);
678
679 end loop;
680
681 wait for 4*clock_period;
682 CLK_STOP <= '1';
683
684 writetimestamp(oline, CLK_CYCLE, ": DONE ");
685 writeline(output, oline);
686
687 wait; -- suspend proc_stim forever
688 -- clock is stopped, sim will end
689
690 end process proc_stim;
691
692 proc_moni: process
693 begin
694
695 loop
696 wait until rising_edge(CLK);
697 wait for c2out_time;
698
699 R_WAITOK <= '0';
700 if R_WAITCMD = '1' then
701 if CP_STAT_cmdack = '1' then
702 R_WAITOK <= '1';
703 end if;
704 elsif R_WAITGO = '1' then
705 if CP_STAT_cmdbusy='0' and CP_STAT_cpugo='0' then
706 R_WAITOK <= '1';
707 end if;
708 elsif R_WAITSTEP = '1' then
709 if CP_STAT_cmdbusy='0' and CP_STAT_cpustep='0' then
710 R_WAITOK <= '1';
711 end if;
712 end if;
713
714 R_CP_STAT.cmdbusy <= CP_STAT_cmdbusy;
715 R_CP_STAT.cmdack <= CP_STAT_cmdack;
716 R_CP_STAT.cmderr <= CP_STAT_cmderr;
717 R_CP_STAT.cmdmerr <= CP_STAT_cmdmerr;
718 R_CP_STAT.cpugo <= CP_STAT_cpugo;
719 R_CP_STAT.cpustep <= CP_STAT_cpustep;
720 R_CP_STAT.cpuwait <= CP_STAT_cpuwait;
721 R_CP_STAT.cpususp <= CP_STAT_cpususp;
722 R_CP_STAT.cpurust <= CP_STAT_cpurust;
723 R_CP_STAT.suspint <= CP_STAT_suspint;
724 R_CP_STAT.suspext <= CP_STAT_suspext;
725 R_CP_DOUT <= CP_DOUT;
726
727 end loop;
728
729 end process proc_moni;
730
731end sim;
pdp11_sim
Definition: pdp11_sim.vhd:23
pdp11
Definition: pdp11.vhd:123
simclk.CLK
out CLK slbit
Definition: simclk.vhd:33
simclk.OFFSET
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
simclk.CLK_STOP
in CLK_STOP slbit := '0'
Definition: simclk.vhd:35
simclk.PERIOD
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
simclkcnt.CLK_CYCLE
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
simclkcnt.CLK
in CLK slbit
Definition: simclkcnt.vhd:27
slvtypes.slv22_1
std_logic_vector( 21 downto 1) slv22_1
Definition: slvtypes.vhd:69
slvtypes.slv4
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
slvtypes.slv5
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
slvtypes.slv3
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
slvtypes.slv16
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
slvtypes.slbit
std_logic slbit
Definition: slvtypes.vhd:30
slvtypes.slv2
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
slvtypes.slv
std_logic_vector slv
Definition: slvtypes.vhd:31
tb_pdp11core.sim
Definition: tb_pdp11core.vhd:91
tb_pdp11core.sim.CP_STAT_suspint
slbit := '0' CP_STAT_suspint
Definition: tb_pdp11core.vhd:114
tb_pdp11core.sim.RESET
slbit := '0' RESET
Definition: tb_pdp11core.vhd:94
tb_pdp11core.sim.R_WAITCMD
slbit := '0' R_WAITCMD
Definition: tb_pdp11core.vhd:125
tb_pdp11core.sim.R_CHKMSK
slv16 :=( others => '0') R_CHKMSK
Definition: tb_pdp11core.vhd:122
tb_pdp11core.sim.CP_STAT_suspext
slbit := '0' CP_STAT_suspext
Definition: tb_pdp11core.vhd:115
tb_pdp11core.sim.R_CP_DOUT
slv16 :=( others => '0') R_CP_DOUT
Definition: tb_pdp11core.vhd:130
tb_pdp11core.sim.CP_ADDR_ena_22bit
slbit := '0' CP_ADDR_ena_22bit
Definition: tb_pdp11core.vhd:102
tb_pdp11core.sim.CP_STAT_cmdack
slbit := '0' CP_STAT_cmdack
Definition: tb_pdp11core.vhd:106
tb_pdp11core.sim.CP_ADDR_racc
slbit := '0' CP_ADDR_racc
Definition: tb_pdp11core.vhd:100
tb_pdp11core.sim.CLK_STOP
slbit := '0' CLK_STOP
Definition: tb_pdp11core.vhd:118
tb_pdp11core.sim.CP_ADDR_be
slv2 := "11" CP_ADDR_be
Definition: tb_pdp11core.vhd:101
tb_pdp11core.sim.R_CHKDAT
slv16 :=( others => '0') R_CHKDAT
Definition: tb_pdp11core.vhd:121
tb_pdp11core.sim.CP_DOUT
slv16 :=( others => '0') CP_DOUT
Definition: tb_pdp11core.vhd:116
tb_pdp11core.sim.CP_STAT_cpususp
slbit := '0' CP_STAT_cpususp
Definition: tb_pdp11core.vhd:112
tb_pdp11core.sim.UNUSEDSIGNAL
slbit := '0' UNUSEDSIGNAL
Definition: tb_pdp11core.vhd:95
tb_pdp11core.sim.CP_DIN
slv16 :=( others => '0') CP_DIN
Definition: tb_pdp11core.vhd:104
tb_pdp11core.sim.CP_ADDR_ena_ubmap
slbit := '0' CP_ADDR_ena_ubmap
Definition: tb_pdp11core.vhd:103
tb_pdp11core.sim.R_WAITOK
slbit := '0' R_WAITOK
Definition: tb_pdp11core.vhd:128
tb_pdp11core.sim.CP_STAT_cmderr
slbit := '0' CP_STAT_cmderr
Definition: tb_pdp11core.vhd:107
tb_pdp11core.sim.CLK
slbit := '0' CLK
Definition: tb_pdp11core.vhd:93
tb_pdp11core.sim.CP_STAT_cmdmerr
slbit := '0' CP_STAT_cmdmerr
Definition: tb_pdp11core.vhd:108
tb_pdp11core.sim.CP_STAT_cmdbusy
slbit := '0' CP_STAT_cmdbusy
Definition: tb_pdp11core.vhd:105
tb_pdp11core.sim.CLK_CYCLE
integer := 0 CLK_CYCLE
Definition: tb_pdp11core.vhd:119
tb_pdp11core.sim.CP_CNTL_func
slv5 :=( others => '0') CP_CNTL_func
Definition: tb_pdp11core.vhd:97
tb_pdp11core.sim.R_WAITGO
slbit := '0' R_WAITGO
Definition: tb_pdp11core.vhd:127
tb_pdp11core.sim.CP_CNTL_rnum
slv3 :=( others => '0') CP_CNTL_rnum
Definition: tb_pdp11core.vhd:98
tb_pdp11core.sim.R_CHKREQ
slbit := '0' R_CHKREQ
Definition: tb_pdp11core.vhd:123
tb_pdp11core.sim.CP_ADDR_addr
slv22_1 :=( others => '0') CP_ADDR_addr
Definition: tb_pdp11core.vhd:99
tb_pdp11core.sim.CP_STAT_cpugo
slbit := '0' CP_STAT_cpugo
Definition: tb_pdp11core.vhd:109
tb_pdp11core.sim.R_CP_STAT
cp_stat_type := cp_stat_init R_CP_STAT
Definition: tb_pdp11core.vhd:129
tb_pdp11core.sim.CP_CNTL_req
slbit := '0' CP_CNTL_req
Definition: tb_pdp11core.vhd:96
tb_pdp11core.sim.CP_STAT_cpuwait
slbit := '0' CP_STAT_cpuwait
Definition: tb_pdp11core.vhd:111
tb_pdp11core.sim.CP_STAT_cpurust
slv4 :=( others => '0') CP_STAT_cpurust
Definition: tb_pdp11core.vhd:113
tb_pdp11core.sim.CP_STAT_cpustep
slbit := '0' CP_STAT_cpustep
Definition: tb_pdp11core.vhd:110
tb_pdp11core.sim.R_WAITSTEP
slbit := '0' R_WAITSTEP
Definition: tb_pdp11core.vhd:126
tb_pdp11core
Definition: tb_pdp11core.vhd:88
tbd_pdp11core
Definition: tbd_pdp11core.vhd:73
tbd_pdp11core.CP_STAT_cmdbusy
out CP_STAT_cmdbusy slbit
Definition: tbd_pdp11core.vhd:86
tbd_pdp11core.CP_CNTL_req
in CP_CNTL_req slbit
Definition: tbd_pdp11core.vhd:77
tbd_pdp11core.RESET
in RESET slbit
Definition: tbd_pdp11core.vhd:76
tbd_pdp11core.CP_STAT_suspint
out CP_STAT_suspint slbit
Definition: tbd_pdp11core.vhd:95
tbd_pdp11core.CP_ADDR_racc
in CP_ADDR_racc slbit
Definition: tbd_pdp11core.vhd:81
tbd_pdp11core.CP_STAT_cpugo
out CP_STAT_cpugo slbit
Definition: tbd_pdp11core.vhd:90
tbd_pdp11core.CP_ADDR_ena_22bit
in CP_ADDR_ena_22bit slbit
Definition: tbd_pdp11core.vhd:83
tbd_pdp11core.CP_STAT_cpuwait
out CP_STAT_cpuwait slbit
Definition: tbd_pdp11core.vhd:92
tbd_pdp11core.CP_STAT_suspext
out CP_STAT_suspext slbit
Definition: tbd_pdp11core.vhd:96
tbd_pdp11core.CP_CNTL_func
in CP_CNTL_func slv5
Definition: tbd_pdp11core.vhd:78
tbd_pdp11core.CLK
in CLK slbit
Definition: tbd_pdp11core.vhd:75
tbd_pdp11core.CP_STAT_cmderr
out CP_STAT_cmderr slbit
Definition: tbd_pdp11core.vhd:88
tbd_pdp11core.CP_STAT_cmdmerr
out CP_STAT_cmdmerr slbit
Definition: tbd_pdp11core.vhd:89
tbd_pdp11core.CP_DOUT
out CP_DOUT slv16
Definition: tbd_pdp11core.vhd:98
tbd_pdp11core.CP_DIN
in CP_DIN slv16
Definition: tbd_pdp11core.vhd:85
tbd_pdp11core.CP_STAT_cpususp
out CP_STAT_cpususp slbit
Definition: tbd_pdp11core.vhd:93
tbd_pdp11core.CP_ADDR_be
in CP_ADDR_be slv2
Definition: tbd_pdp11core.vhd:82
tbd_pdp11core.CP_ADDR_addr
in CP_ADDR_addr slv22_1
Definition: tbd_pdp11core.vhd:80
tbd_pdp11core.CP_CNTL_rnum
in CP_CNTL_rnum slv3
Definition: tbd_pdp11core.vhd:79
tbd_pdp11core.CP_STAT_cpustep
out CP_STAT_cpustep slbit
Definition: tbd_pdp11core.vhd:91
tbd_pdp11core.CP_STAT_cpurust
out CP_STAT_cpurust slv4
Definition: tbd_pdp11core.vhd:94
tbd_pdp11core.CP_ADDR_ena_ubmap
in CP_ADDR_ena_ubmap slbit
Definition: tbd_pdp11core.vhd:84
tbd_pdp11core.CP_STAT_cmdack
out CP_STAT_cmdack slbit
Definition: tbd_pdp11core.vhd:87