70use ieee.std_logic_1164.
all;
71use ieee.numeric_std.
all;
215 if rising_edge(CLK) then
223 end process proc_regs;
229 variable ibusy : slbit := '0';
230 variable iackw : slbit := '0';
231 variable iactr : slbit := '0';
232 variable iactw : slbit := '0';
233 variable imem_ce : slbit := '0';
234 variable imem_we : slbit := '0';
235 variable imem_oe : slbit := '0';
236 variable iaddrw_ce : slbit := '0';
237 variable iaddrb : slv2 := "00";
238 variable iaddrb_be : slv2 := "00";
239 variable iaddrb_ce : slbit := '0';
240 variable idata_cei : slbit := '0';
241 variable idata_ceo : slbit := '0';
242 variable idata_oe : slbit := '0';
243 variable imem_di : slv8 := "00000000";
267 imem_di := "00000000";
268 if r.be(0) = '1' then
270 imem_di := r.memdi( 7 downto 0);
271 elsif r.be(1) = '1' then
273 imem_di := r.memdi(15 downto 8);
274 elsif r.be(2) = '1' then
276 imem_di := r.memdi(23 downto 16);
277 elsif r.be(3) = '1' then
279 imem_di := r.memdi(31 downto 24);
305 when "00" => n.addrb := "01";
306 when "01" => n.addrb := "10";
n.memdo( 7 downto 0) := MEM_DO;
307 when "10" => n.addrb := "11";
n.memdo(15 downto 8) := MEM_DO;
308 when "11" => n.addrb := "00";
n.memdo(23 downto 16) := MEM_DO;
317 if r.addrb = "00" then
339 if r.be = "0000" then
348 n.be(to_integer(unsigned(iaddrb_be))) := '0';
375 end process proc_next;
slv8 := "00000000" MEM_DI
regs_type :=( s_idle, "00", "0000",( others => '0'),( others => '0'), '0') regs_init
slv8 := "00000000" MEM_DO
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
(s_idle,s_read0,s_read1,s_write0,s_write1) state_type
inout PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
out DI slv( DWIDTH- 1 downto 0)
out PAD slv( DWIDTH- 1 downto 0)
in DO slv( DWIDTH- 1 downto 0)
std_logic_vector( 18 downto 0) slv19
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 16 downto 0) slv17
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 23 downto 0) slv24
std_logic_vector( 1 downto 0) slv2