48use ieee.std_logic_1164.
all;
49use ieee.numeric_std.
all;
69 proc_cnt:
process (
CLK)
72 if rising_edge(CLK) then
74 R_CNT <= (others=>'0');
91use ieee.std_logic_1164.
all;
176 ADDR => R_REGS.saddr,
181 PRE: for i in 31 downto 0 generate
182 ENA: if CENA(i)='1' generate
187 ENA => R_REGS.psig
(i
),
194 variable iclr : slv32 := (others=>'0');
195 variable ipdo : slv32 := (others=>'0');
196 variable icnt : slv32 := (others=>'0');
197 variable imdi : slv32 := (others=>'0');
198 constant ipdo_pad
: slv(31 downto 5) := (others=>'0');
199 constant icnt_pad
: slv(31 downto 1) := (others=>'0');
201 iclr := (others=>'0');
202 iclr(to_integer(unsigned(R_REGS.saddr))) := '1';
204 ipdo := ipdo_pad & PRE_DO(to_integer(unsigned(R_REGS.saddr)));
205 icnt := icnt_pad & R_REGS.psig(to_integer(unsigned(R_REGS.saddr)));
207 if R_REGS.zbusy = '0' then
208 imdi := slv(unsigned(MEM_DO) + unsigned(ipdo) + unsigned(icnt));
210 imdi := (others=>'0');
214 end process proc_cnt;
219 if rising_edge(CLK) then
227 end process proc_regs;
234 variable irb_ack : slbit := '0';
235 variable irb_busy : slbit := '0';
236 variable irb_err : slbit := '0';
237 variable irb_dout : slv16 := (others=>'0');
238 variable irbena : slbit := '0';
248 irb_dout := (others=>'0');
262 n.psig := (others=>'0');
265 n.saddr := slv(unsigned(r.saddr) + 1);
270 if r.saddr = r.raddr and r.waddr = '0' and
271 (r.dval='0' or r.rbsel='0') then
277 if r.rbsel = '1' then
279 case RB_MREQ.addr(1 downto 0) is
292 if r.zbusy = '0' then
294 n.saddr := (others=>'0');
295 n.raddr := (others=>'0');
300 if r.saddr = "11111" then
330 n.waddr := not r.waddr;
331 if r.ainc='1' and r.waddr = '1' then
332 n.raddr := slv(unsigned(r.raddr) + 1);
338 when others => irb_err := '1';
343 if r.rbsel = '1' then
344 case RB_MREQ.addr(1 downto 0) is
356 if r.waddr = '0' then
357 irb_dout := r.dout(15 downto 0);
359 irb_dout := r.dout(31 downto 16);
373 end process proc_next;
slv32 :=( others => '0') MEM_DI
integer range 7 downto 0 cntl_rbf_vers
( 31 downto 0) slv5 pre_do_type
integer range 13 downto 9 stat_rbf_caddr
slv32 :=( others => '0') MEM_DO
regs_type :=( '0', '0',( others => '0'),( others => '0'), '0', '0', '0', '0',( others => '0'),( others => '0')) regs_init
integer range 2 downto 0 cntl_rbf_func
integer range 13 downto 9 cntl_rbf_caddr
integer := 15 cntl_rbf_ainc
slv32 :=( others => '0') PRE_CLR
regs_type := regs_init R_REGS
pre_do_type :=( others =>( others => '0')) PRE_DO
integer := 8 stat_rbf_waddr
integer := 15 stat_rbf_ainc
integer := 0 stat_rbf_run
slv5 :=( others => '0') R_CNT
CENA slv32 :=( others => '1')
VERS slv8 := slv( to_unsigned( 1, 8) )
RB_ADDR slv16 := rbaddr_dmpcnt_off
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2