42use ieee.std_logic_1164.
all;
43use ieee.numeric_std.
all;
94 scnt : slv(35 downto 0);
138 ADDRB => R_REGS.snum1,
148 if rising_edge(CLK) then
156 end process proc_regs;
165 variable irb_ack : slbit := '0';
166 variable irb_busy : slbit := '0';
167 variable irb_err : slbit := '0';
168 variable irb_dout : slv16 := (others=>'0');
169 variable irbena : slbit := '0';
171 variable icea : slbit := '0';
172 variable iwea : slbit := '0';
173 variable iweb : slbit := '0';
174 variable iaddra : slv9 := (others=>'0');
175 variable iscnt0 : slv(35 downto 0) := (others=>'0');
176 variable iscnt1 : slv(35 downto 0) := (others=>'0');
186 irb_dout := (others=>'0');
206 if r.rbsel = '1' then
209 case RB_MREQ.addr(1 downto 0) is
215 n.laddr := (others=>'0');
226 n.waddr := (others=>'0');
248 n.laddr := slv(unsigned(r.laddr) + 1);
270 if r.rbsel = '1' then
271 case RB_MREQ.addr(1 downto 0) is
280 when "00" => irb_dout := CMEM_DOA(15 downto 0);
281 when "01" => irb_dout := r.mbuf(15 downto 0);
282 when "10" => irb_dout(3 downto 0) := r.mbuf(19 downto 16);
301 if r.snum0=r.snum1 and r.ena1 ='1' then
313 iscnt1 := slv(unsigned(iscnt0) + 1);
322 n.laddr := slv(unsigned(r.laddr) + 1);
323 if r.laddr = "111111111" then
326 elsif r.ena1 = '1' then
344 end process proc_next;
slv( 35 downto 0) :=( others => '0') CMEM_DIB
regs_type :=( s_idle, '0', '0', '0', '0',( others => '0'),( others => '0'), '0',( others => '0'),( others => '0'),( others => '0'),( others => '0')) regs_init
(s_idle,s_mread) state_type
integer := 0 cntl_rbf_ena
integer range 10 downto 2 addr_rbf_mem
slv( 35 downto 0) :=( others => '0') cmem_data_zero
slv( 35 downto 0) :=( others => '0') CMEM_DOA
integer := 1 cntl_rbf_clr
slv9 :=( others => '0') CMEM_ADDRA
integer range 1 downto 0 addr_rbf_word
regs_type := regs_init R_REGS
in DM_STAT_DP dm_stat_dp_type
in DM_STAT_CO dm_stat_co_type
in DM_STAT_SE dm_stat_se_type
RB_ADDR slv16 := rbaddr_dmscnt_off
in DIA slv( DWIDTH- 1 downto 0)
in ADDRB slv( AWIDTH- 1 downto 0)
in ADDRA slv( AWIDTH- 1 downto 0)
out DOB slv( DWIDTH- 1 downto 0)
in DIB slv( DWIDTH- 1 downto 0)
out DOA slv( DWIDTH- 1 downto 0)
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 8 downto 0) slv9
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 1 downto 0) slv2