35use ieee.std_logic_1164.
all;
36use ieee.numeric_std.
all;
108 DI => IB_MREQ.din
(ibf_byte1
),
119 DI => IB_MREQ.din
(ibf_byte0
),
158 variable ibsel_dr : slbit := '0';
159 variable ibsel_ar : slbit := '0';
161 if rising_edge(CLK) then
178 end process proc_ibsel;
181 variable parout : slv16 := (others=>'0');
182 variable pdrout : slv16 := (others=>'0');
185 parout := (others=>'0');
190 pdrout := (others=>'0');
197 IB_SRES.dout <= parout or pdrout;
202 end process proc_ibres;
211 variable eaddr : slv6 := (others=>'0');
212 variable idr : slbit := '0';
213 variable iar : slbit := '0';
221 eaddr(4) := not IB_MREQ.addr(6);
222 eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
227 end process proc_eaddr;
277 end process proc_comb;
slv16 := slv( to_unsigned( 8#172200#, 16) ) ibaddr_smdar
slv16 := slv( to_unsigned( 8#177600#, 16) ) ibaddr_umdar
slv6 :=( others => '0') PADR_ADDR
slv16 := slv( to_unsigned( 8#172300#, 16) ) ibaddr_kmdar
slv16 :=( others => '0') PAF
integer range 14 downto 8 pdr_ibf_plf
integer range 7 downto 6 pdr_ibf_aib
slv7 :=( others => '0') PLF
integer range 3 downto 0 pdr_ibf_acf
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 5 downto 0) slv6
std_logic_vector( 1 downto 0) slv2