w11 - vhd 0.794
W11 CPU core and support modules
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pdp11_ubmap.vhd
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1-- $Id: pdp11_ubmap.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2008-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: pdp11_ubmap - syn
7-- Description: pdp11: 11/70 unibus mapper
8--
9-- Dependencies: memlib/ram_1swar_gen
10-- ib_sel
11-- Test bench: tb/tb_pdp11_core (implicit)
12-- Target Devices: generic
13-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
14--
15-- Revision History:
16-- Date Rev Version Comment
17-- 2011-11-18 427 1.1.2 now numeric_std clean
18-- 2010-10-23 335 1.1.1 use ib_sel
19-- 2010-10-17 333 1.1 use ibus V2 interface
20-- 2008-08-22 161 1.0.1 use iblib
21-- 2008-01-27 115 1.0 Initial version
22------------------------------------------------------------------------------
23
24library ieee;
25use ieee.std_logic_1164.all;
26use ieee.numeric_std.all;
27
28use work.slvtypes.all;
29use work.memlib.all;
30use work.iblib.all;
31use work.pdp11.all;
32
33-- ----------------------------------------------------------------------------
34
35entity pdp11_ubmap is -- 11/70 unibus mapper
36 port (
37 CLK : in slbit; -- clock
38 MREQ : in slbit; -- request mapping
39 ADDR_UB : in slv18_1; -- UNIBUS address (in)
40 ADDR_PM : out slv22_1; -- physical memory address (out)
41 IB_MREQ : in ib_mreq_type; -- ibus request
42 IB_SRES : out ib_sres_type -- ibus response
43 );
44end pdp11_ubmap;
45
46architecture syn of pdp11_ubmap is
47
48 constant ibaddr_ubmap : slv16 := slv(to_unsigned(8#170200#,16));
49
50 signal IBSEL_UBMAP : slbit := '0';
51
52 signal MAP_2_WE : slbit := '0';
53 signal MAP_1_WE : slbit := '0';
54 signal MAP_0_WE : slbit := '0';
55 signal MAP_ADDR : slv5 := (others => '0'); -- map regs address
56 signal MAP_DOUT : slv22_1 := (others => '0'); -- map regs output
57
58begin
59
60 MAP_2 : ram_1swar_gen -- bit 21:16 of map regs
61 generic map (
62 AWIDTH => 5,
63 DWIDTH => 6)
64 port map (
65 CLK => CLK,
66 WE => MAP_2_WE,
67 ADDR => MAP_ADDR,
68 DI => IB_MREQ.din(5 downto 0),
69 DO => MAP_DOUT(21 downto 16));
70
71 MAP_1 : ram_1swar_gen -- bit 15:08 of map regs
72 generic map (
73 AWIDTH => 5,
74 DWIDTH => 8)
75 port map (
76 CLK => CLK,
77 WE => MAP_1_WE,
78 ADDR => MAP_ADDR,
79 DI => IB_MREQ.din(15 downto 8),
80 DO => MAP_DOUT(15 downto 8));
81
82 MAP_0 : ram_1swar_gen -- bit 07:01 of map regs
83 generic map (
84 AWIDTH => 5,
85 DWIDTH => 7)
86 port map (
87 CLK => CLK,
88 WE => MAP_0_WE,
89 ADDR => MAP_ADDR,
90 DI => IB_MREQ.din(7 downto 1),
91 DO => MAP_DOUT(7 downto 1));
92
93 SEL : ib_sel
94 generic map (
96 SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
97 port map (
98 CLK => CLK,
101 );
102
103 proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
104 variable ibusy : slbit := '0';
105 variable idout : slv16 := (others=>'0');
106 variable iwe2 : slbit := '0';
107 variable iwe1 : slbit := '0';
108 variable iwe0 : slbit := '0';
109 variable iaddr : slv5 := (others=>'0');
110 begin
111
112 ibusy := '0';
113 idout := (others=>'0');
114 iwe2 := '0';
115 iwe1 := '0';
116 iwe0 := '0';
117 iaddr := (others=>'0');
118
119 if IBSEL_UBMAP = '1' then
120 if IB_MREQ.addr(1) = '1' then
121 idout(5 downto 0) := MAP_DOUT(21 downto 16);
122 else
123 idout(15 downto 1) := MAP_DOUT(15 downto 1);
124 end if;
125 if MREQ = '1' then -- if map request, stall ib cycle
126 ibusy := '1';
127 end if;
128 end if;
129
130 if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
131 if IB_MREQ.addr(1)='1' then
132 if IB_MREQ.be0 = '1' then
133 iwe2 := '1';
134 end if;
135 else
136 if IB_MREQ.be1 = '1' then
137 iwe1 := '1';
138 end if;
139 if IB_MREQ.be0 = '1' then
140 iwe0 := '1';
141 end if;
142 end if;
143 end if;
144
145 if MREQ = '1' then
146 iaddr := ADDR_UB(17 downto 13);
147 else
148 iaddr := IB_MREQ.addr(6 downto 2);
149 end if;
150
151 MAP_ADDR <= iaddr;
152 MAP_2_WE <= iwe2;
153 MAP_1_WE <= iwe1;
154 MAP_0_WE <= iwe0;
155
156 ADDR_PM <= slv(unsigned(MAP_DOUT) +
157 unsigned("000000000"&ADDR_UB(12 downto 1)));
158
159 IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
160 IB_SRES.busy <= ibusy;
161 IB_SRES.dout <= idout;
162
163 end process proc_comb;
164
165end syn;
out SEL slbit
Definition: ib_sel.vhd:35
IB_ADDR slv16
Definition: ib_sel.vhd:29
SAWIDTH natural := 0
Definition: ib_sel.vhd:30
in CLK slbit
Definition: ib_sel.vhd:32
in IB_MREQ ib_mreq_type
Definition: ib_sel.vhd:33
Definition: iblib.vhd:33
slbit := '0' MAP_2_WE
Definition: pdp11_ubmap.vhd:52
slbit := '0' MAP_0_WE
Definition: pdp11_ubmap.vhd:54
slv22_1 :=( others => '0') MAP_DOUT
Definition: pdp11_ubmap.vhd:56
slv16 := slv( to_unsigned( 8#170200#, 16) ) ibaddr_ubmap
Definition: pdp11_ubmap.vhd:48
slv5 :=( others => '0') MAP_ADDR
Definition: pdp11_ubmap.vhd:55
slbit := '0' IBSEL_UBMAP
Definition: pdp11_ubmap.vhd:50
slbit := '0' MAP_1_WE
Definition: pdp11_ubmap.vhd:53
out ADDR_PM slv22_1
Definition: pdp11_ubmap.vhd:40
in CLK slbit
Definition: pdp11_ubmap.vhd:37
in ADDR_UB slv18_1
Definition: pdp11_ubmap.vhd:39
in MREQ slbit
Definition: pdp11_ubmap.vhd:38
in IB_MREQ ib_mreq_type
Definition: pdp11_ubmap.vhd:41
out IB_SRES ib_sres_type
Definition: pdp11_ubmap.vhd:43
Definition: pdp11.vhd:123
std_logic_vector( 21 downto 1) slv22_1
Definition: slvtypes.vhd:69
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 17 downto 1) slv18_1
Definition: slvtypes.vhd:68
std_logic_vector slv
Definition: slvtypes.vhd:31