40use ieee.std_logic_1164.
all;
41use ieee.numeric_std.
all;
106 if rising_edge(CLK) then
113 end process proc_regs;
118 variable irb_ack : slbit := '0';
119 variable irb_busy : slbit := '0';
120 variable irb_dout : slv16 := (others=>'0');
121 variable irbena : slbit := '0';
122 variable isbusy : slbit := '0';
123 variable ibramen : slbit := '0';
124 variable ibramwe : slbit := '0';
132 irb_dout := (others=>'0');
137 if unsigned(r.cntbusy) /= 0 then
152 n.cntbusy := r.nbusy;
158 if r.rbsel = '1' then
161 if unsigned(r.cntbusy) /= 0 then
162 n.cntbusy := slv(unsigned(r.cntbusy) - 1);
168 case RB_MREQ.addr(0 downto 0) is
177 irb_busy := irbena and isbusy;
183 n.addr := slv(unsigned(r.addr) + 1);
192 if r.rbsel = '1' then
193 case RB_MREQ.addr(0 downto 0) is
213 end process proc_next;
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
regs_type :=( '0',( others => '0'),( others => '0'),( others => '0')) regs_init
regs_type := regs_init N_REGS
integer range 9 downto 0 cntl_rbf_addr
integer range 15 downto 10 cntl_rbf_nbusy
slv16 :=( others => '0') BRAM_DO
regs_type := regs_init R_REGS
RB_ADDR slv16 :=( others => '0')
std_logic_vector( 9 downto 0) slv10
std_logic_vector( 0 downto 0) slv1
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 5 downto 0) slv6