w11 - vhd 0.794
W11 CPU core and support modules
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rbd_bram.vhd
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1-- $Id: rbd_bram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rbd_bram - syn
7-- Description: rbus dev: rbus bram test target
8--
9-- Dependencies: memlib/ram_1swsr_wfirst_gen
10--
11-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
12--
13-- Target Devices: generic
14-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
15--
16-- Synthesized (xst):
17-- Date Rev ise Target flop lutl lutm slic t peri
18-- 2010-12-26 349 12.1 M53d xc3s1000-4 23 61 - 34 s 6.3
19--
20-- Revision History:
21-- Date Rev Version Comment
22-- 2014-09-13 593 4.1 no default rbus addess anymore, def=0
23-- 2014-08-15 583 4.0 rb_mreq addr now 16 bit
24-- 2011-11-19 427 1.0.3 now numeric_std clean
25-- 2010-12-31 352 1.0.2 simplify irb_ack logic
26-- 2010-12-29 351 1.0.1 default addr 1111001x->1111010x
27-- 2010-12-26 349 1.0 Initial version
28------------------------------------------------------------------------------
29--
30-- rbus registers:
31--
32-- Addr Bits Name r/w/f Function
33-- 0 cntl r/w/- Control register
34-- 15:10 nbusy r/w/- busy cycles
35-- 9:00 addr r/w/- bram address (will auto-increment)
36-- 1 15:00 data r/w/- Data register (read/write to bram via addr)
37--
38
39library ieee;
40use ieee.std_logic_1164.all;
41use ieee.numeric_std.all;
42
43use work.slvtypes.all;
44use work.memlib.all;
45use work.rblib.all;
46
47entity rbd_bram is -- rbus dev: rbus bram test target
48 -- complete rrirp_aif interface
49 generic (
50 RB_ADDR : slv16 := (others=>'0'));
51 port (
52 CLK : in slbit; -- clock
53 RESET : in slbit; -- reset
54 RB_MREQ : in rb_mreq_type; -- rbus: request
55 RB_SRES : out rb_sres_type -- rbus: response
56 );
57end entity rbd_bram;
58
59
60architecture syn of rbd_bram is
61
62 constant rbaddr_cntl : slv1 := "0"; -- cntl address offset
63 constant rbaddr_data : slv1 := "1"; -- data address offset
64
65 subtype cntl_rbf_nbusy is integer range 15 downto 10;
66 subtype cntl_rbf_addr is integer range 9 downto 0;
67
68 type regs_type is record -- state registers
69 rbsel : slbit; -- rbus select
70 addr : slv10; -- addr register
71 nbusy : slv6; -- nbusy setting
72 cntbusy : slv6; -- busy timer
73 end record regs_type;
74
75 constant regs_init : regs_type := (
76 '0', -- rbsel
77 (others=>'0'), -- addr
78 (others=>'0'), -- nbusy
79 (others=>'0') -- cntbusy
80 );
81
84
85 signal BRAM_EN : slbit := '0';
86 signal BRAM_WE : slbit := '0';
87 signal BRAM_DO : slv16 := (others=>'0');
88
89begin
90
92 generic map (
93 AWIDTH => 10,
94 DWIDTH => 16)
95 port map (
96 CLK => CLK,
97 EN => BRAM_EN,
98 WE => BRAM_WE,
99 ADDR => R_REGS.addr,
100 DI => RB_MREQ.din,
101 DO => BRAM_DO
102 );
103
104 proc_regs: process (CLK)
105 begin
106 if rising_edge(CLK) then
107 if RESET = '1' then
108 R_REGS <= regs_init;
109 else
110 R_REGS <= N_REGS;
111 end if;
112 end if;
113 end process proc_regs;
114
115 proc_next : process (R_REGS, RB_MREQ, BRAM_DO)
116 variable r : regs_type := regs_init;
117 variable n : regs_type := regs_init;
118 variable irb_ack : slbit := '0';
119 variable irb_busy : slbit := '0';
120 variable irb_dout : slv16 := (others=>'0');
121 variable irbena : slbit := '0';
122 variable isbusy : slbit := '0';
123 variable ibramen : slbit := '0';
124 variable ibramwe : slbit := '0';
125 begin
126
127 r := R_REGS;
128 n := R_REGS;
129
130 irb_ack := '0';
131 irb_busy := '0';
132 irb_dout := (others=>'0');
133
134 irbena := RB_MREQ.re or RB_MREQ.we;
135
136 isbusy := '0';
137 if unsigned(r.cntbusy) /= 0 then
138 isbusy := '1';
139 end if;
140
141 ibramen := '0';
142 ibramwe := '0';
143
144 -- rbus address decoder
145 n.rbsel := '0';
146 if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 1)=RB_ADDR(15 downto 1) then
147
148 n.rbsel := '1';
149 ibramen := '1';
150
151 if irbena = '0' then -- addr valid and selected, but no req
152 n.cntbusy := r.nbusy; -- preset busy timer
153 end if;
154
155 end if;
156
157 -- rbus transactions
158 if r.rbsel = '1' then
159
160 if irbena = '1' then -- if request active
161 if unsigned(r.cntbusy) /= 0 then -- if busy timer > 0
162 n.cntbusy := slv(unsigned(r.cntbusy) - 1); -- decrement busy timer
163 end if;
164 end if;
165
166 irb_ack := irbena; -- ack all accesses
167
168 case RB_MREQ.addr(0 downto 0) is
169
170 when rbaddr_cntl =>
171 if RB_MREQ.we = '1' then
172 n.nbusy := RB_MREQ.din(cntl_rbf_nbusy);
173 n.addr := RB_MREQ.din(cntl_rbf_addr);
174 end if;
175
176 when rbaddr_data =>
177 irb_busy := irbena and isbusy;
178 if isbusy = '0' then
179 if RB_MREQ.we = '1' then
180 ibramwe := '1';
181 end if;
182 if irbena = '1' then
183 n.addr := slv(unsigned(r.addr) + 1);
184 end if;
185 end if;
186
187 when others => null;
188 end case;
189 end if;
190
191 -- rbus output driver
192 if r.rbsel = '1' then
193 case RB_MREQ.addr(0 downto 0) is
194 when rbaddr_cntl =>
195 irb_dout(cntl_rbf_nbusy) := r.nbusy;
196 irb_dout(cntl_rbf_addr) := r.addr;
197 when rbaddr_data =>
198 irb_dout := BRAM_DO;
199 when others => null;
200 end case;
201 end if;
202
203 N_REGS <= n;
204
205 BRAM_EN <= ibramen;
206 BRAM_WE <= ibramwe;
207
208 RB_SRES.dout <= irb_dout;
209 RB_SRES.ack <= irb_ack;
210 RB_SRES.err <= '0';
211 RB_SRES.busy <= irb_busy;
212
213 end process proc_next;
214
215end syn;
in ADDR slv( AWIDTH- 1 downto 0)
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
regs_type :=( '0',( others => '0'),( others => '0'),( others => '0')) regs_init
Definition: rbd_bram.vhd:75
slv1 := "0" rbaddr_cntl
Definition: rbd_bram.vhd:62
slbit := '0' BRAM_EN
Definition: rbd_bram.vhd:85
regs_type := regs_init N_REGS
Definition: rbd_bram.vhd:83
integer range 9 downto 0 cntl_rbf_addr
Definition: rbd_bram.vhd:66
integer range 15 downto 10 cntl_rbf_nbusy
Definition: rbd_bram.vhd:65
slbit := '0' BRAM_WE
Definition: rbd_bram.vhd:86
slv16 :=( others => '0') BRAM_DO
Definition: rbd_bram.vhd:87
regs_type := regs_init R_REGS
Definition: rbd_bram.vhd:82
slv1 := "1" rbaddr_data
Definition: rbd_bram.vhd:63
in RESET slbit
Definition: rbd_bram.vhd:53
in CLK slbit
Definition: rbd_bram.vhd:52
in RB_MREQ rb_mreq_type
Definition: rbd_bram.vhd:54
RB_ADDR slv16 :=( others => '0')
Definition: rbd_bram.vhd:50
out RB_SRES rb_sres_type
Definition: rbd_bram.vhd:56
Definition: rblib.vhd:32
std_logic_vector( 9 downto 0) slv10
Definition: slvtypes.vhd:42
std_logic_vector( 0 downto 0) slv1
Definition: slvtypes.vhd:33
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 5 downto 0) slv6
Definition: slvtypes.vhd:38
std_logic_vector slv
Definition: slvtypes.vhd:31