w11 - vhd 0.794
W11 CPU core and support modules
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sysmonx_rbus_base.vhd
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1-- $Id: sysmonx_rbus_base.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sysmonx_rbus_base - syn
7-- Description: 7series XADC interface to rbus (basic supply monitor version)
8--
9-- Dependencies: sysmon_rbus_core
10--
11-- Test bench: -
12--
13-- Target Devices: 7series
14-- Tool versions: viv 2015.4-2019.1; ghdl 0.33-0.35
15--
16-- Revision History:
17-- Date Rev Version Comment
18-- 2016-03-13 742 1.0 Initial version
19-- 2016-03-06 738 0.1 First draft
20------------------------------------------------------------------------------
21--
22-- rbus registers: see sysmon_rbus_core and XADC user guide
23--
24-- XADC usage:
25-- - only build-in sensors: temp, Vccint, Vccaux, Vccbram
26--
27
28library ieee;
29use ieee.std_logic_1164.all;
30use ieee.numeric_std.all;
31
32library unisim;
33use unisim.vcomponents.ALL;
34
35use work.slvtypes.all;
36use work.rblib.all;
37use work.sysmonrbuslib.all;
38
39-- ----------------------------------------------------------------------------
40
41entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
42 generic (
43 INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
44 INIT_TEMP_LOW : real := 60.0; -- INIT_54
45 INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
46 INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
47 INIT_VCCAUX_UP : real := 1.89; -- INIT_52
48 INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
49 INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
50 INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
51 CLK_MHZ : integer := 250; -- clock frequency in MHz
52 RB_ADDR : slv16 := x"fb00");
53 port (
54 CLK : in slbit; -- clock
55 RESET : in slbit := '0'; -- reset
56 RB_MREQ : in rb_mreq_type; -- rbus: request
57 RB_SRES : out rb_sres_type; -- rbus: response
58 ALM : out slv8; -- xadc: alarms
59 OT : out slbit; -- xadc: over temp
60 TEMP : out slv12 -- xadc: die temp
61 );
63
64architecture syn of sysmonx_rbus_base is
65
66 constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
67 constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
68
69 signal SM_DEN : slbit := '0';
70 signal SM_DWE : slbit := '0';
71 signal SM_DADDR : slv7 := (others=>'0');
72 signal SM_DI : slv16 := (others=>'0');
73 signal SM_DO : slv16 := (others=>'0');
74 signal SM_DRDY : slbit := '0';
75 signal SM_EOS : slbit := '0';
76 signal SM_EOC : slbit := '0';
77 signal SM_RESET : slbit := '0';
78 signal SM_CHAN : slv5 := (others=>'0');
79 signal SM_ALM : slv8 := (others=>'0');
80 signal SM_OT : slbit := '0';
81 signal SM_JTAGLOCKED : slbit := '0';
82 signal SM_JTAGMODIFIED : slbit := '0';
83 signal SM_JTAGBUSY : slbit := '0';
84
85begin
86
87 SM : XADC
88 generic map (
89 INIT_40 => xadc_init_40_default, -- conf #0
90 INIT_41 => xadc_init_41_default, -- conf #1
91 INIT_42 => init_42,
92 INIT_43 => x"0000", -- test #0 - don't use, stay 0
93 INIT_44 => x"0000", -- test #1 - "
94 INIT_45 => x"0000", -- test #2 - "
95 INIT_46 => x"0000", -- test #3 - "
96 INIT_47 => x"0000", -- test #4 - "
97 INIT_48 => xadc_init_48_default, -- seq #0: sel 0
98 INIT_49 => x"0000", -- seq #1: sel 1: no aux
99 INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
100 INIT_4B => x"0000", -- seq #3: avr 1: "
101 INIT_4C => x"0000", -- seq #4: mode 0: unipolar
102 INIT_4D => x"0000", -- seq #5: mode 1: "
103 INIT_4E => x"0000", -- seq #6: time 0: fast
104 INIT_4F => x"0000", -- seq #7: time 1: "
105 INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
106 INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
107 INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
108 INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
109 INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
110 INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
111 INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
112 INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
113 INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
114 INIT_59 => x"0000", -- alm #09: ccpint up (4)
115 INIT_5A => x"0000", -- alm #10: ccpaux up (5)
116 INIT_5B => x"0000", -- alm #11: ccdram up (6)
117 INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
118 INIT_5D => x"0000", -- alm #13: ccpint low (4)
119 INIT_5E => x"0000", -- alm #14: ccpaux low (5)
120 INIT_5F => x"0000", -- alm #15: ccdram low (6)
121-- IS_CONVSTCLK_INVERTED => '0',
122-- IS_DCLK_INVERTED => '0',
123 SIM_DEVICE => "7SERIES",
124 SIM_MONITOR_FILE => "sysmon_stim")
125 port map (
126 DCLK => CLK,
127 DEN => SM_DEN,
128 DWE => SM_DWE,
129 DADDR => SM_DADDR,
130 DI => SM_DI,
131 DO => SM_DO,
132 DRDY => SM_DRDY,
133 EOC => SM_EOC, -- connected for tb usage
134 EOS => SM_EOS,
135 BUSY => open,
136 RESET => SM_RESET,
137 CHANNEL => SM_CHAN, -- connected for tb usage
138 MUXADDR => open,
139 ALM => SM_ALM,
140 OT => SM_OT,
141 CONVST => '0',
142 CONVSTCLK => '0',
143 JTAGBUSY => SM_JTAGBUSY,
144 JTAGLOCKED => SM_JTAGLOCKED,
145 JTAGMODIFIED => SM_JTAGMODIFIED,
146 VAUXN => (others=>'0'),
147 VAUXP => (others=>'0'),
148 VN => '0',
149 VP => '0'
150 );
151
152 SMRB : sysmon_rbus_core
153 generic map (
154 DAWIDTH => 7,
155 ALWIDTH => 8,
156 TEWIDTH => 12,
157 IBASE => x"78",
158 RB_ADDR => RB_ADDR)
159 port map (
160 CLK => CLK,
161 RESET => RESET,
162 RB_MREQ => RB_MREQ,
163 RB_SRES => RB_SRES,
164 SM_DEN => SM_DEN,
165 SM_DWE => SM_DWE,
167 SM_DI => SM_DI,
168 SM_DO => SM_DO,
169 SM_DRDY => SM_DRDY,
170 SM_EOS => SM_EOS,
172 SM_ALM => SM_ALM,
173 SM_OT => SM_OT,
177 TEMP => TEMP
178 );
179
180 ALM <= SM_ALM;
181 OT <= SM_OT;
182
183end syn;
Definition: rblib.vhd:32
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 11 downto 0) slv12
Definition: slvtypes.vhd:44
std_logic_vector( 6 downto 0) slv7
Definition: slvtypes.vhd:39
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31
TEWIDTH positive := 12
out SM_DADDR slv( DAWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
in SM_JTAGMODIFIED slbit
DAWIDTH positive := 7
in SM_ALM slv( ALWIDTH- 1 downto 0)
IBASE slv8 := x"78"
out RB_SRES rb_sres_type
out TEMP slv( TEWIDTH- 1 downto 0)
ALWIDTH positive := 8
in RESET slbit := '0'
slv7 :=( others => '0') SM_DADDR
slv16 :=( others => '0') SM_DO
integer :=( CLK_MHZ+ 25)/ 26 conf2_cd
slv5 :=( others => '0') SM_CHAN
bv16 := to_bitvector( slv( to_unsigned( 256* conf2_cd, 16) ) ) init_42
slv8 :=( others => '0') SM_ALM
slv16 :=( others => '0') SM_DI
INIT_VCCINT_LOW real := 0.95
INIT_VCCAUX_UP real := 1.89
INIT_VCCBRAM_LOW real := 0.95
INIT_TEMP_LOW real := 60.0
INIT_VCCBRAM_UP real := 1.05
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
INIT_TEMP_UP real := 85.0
INIT_VCCINT_UP real := 1.05
out RB_SRES rb_sres_type
in RESET slbit := '0'
INIT_VCCAUX_LOW real := 1.71