29use ieee.std_logic_1164.
all;
30use ieee.numeric_std.
all;
33use unisim.vcomponents.
ALL;
89 INIT_40 => xadc_init_40_default,
90 INIT_41 => xadc_init_41_default,
97 INIT_48 => xadc_init_48_default,
99 INIT_4A => xadc_init_4a_default,
108 INIT_53 => xadc_init_53_default,
112 INIT_57 => xadc_init_57_default,
123 SIM_DEVICE =>
"7SERIES",
124 SIM_MONITOR_FILE =>
"sysmon_stim")
146 VAUXN =>
(others=>'0'
),
147 VAUXP =>
(others=>'0'
),
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 11 downto 0) slv12
std_logic_vector( 6 downto 0) slv7
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
out SM_DADDR slv( DAWIDTH- 1 downto 0)
in SM_ALM slv( ALWIDTH- 1 downto 0)
out TEMP slv( TEWIDTH- 1 downto 0)
slv7 :=( others => '0') SM_DADDR
slv16 :=( others => '0') SM_DO
integer :=( CLK_MHZ+ 25)/ 26 conf2_cd
slv5 :=( others => '0') SM_CHAN
bv16 := to_bitvector( slv( to_unsigned( 256* conf2_cd, 16) ) ) init_42
slbit := '0' SM_JTAGMODIFIED
slbit := '0' SM_JTAGLOCKED
slv8 :=( others => '0') SM_ALM
slv16 :=( others => '0') SM_DI
INIT_VCCINT_LOW real := 0.95
INIT_VCCAUX_UP real := 1.89
INIT_VCCBRAM_LOW real := 0.95
INIT_TEMP_LOW real := 60.0
INIT_VCCBRAM_UP real := 1.05
INIT_TEMP_UP real := 85.0
INIT_VCCINT_UP real := 1.05
INIT_VCCAUX_LOW real := 1.71