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W11 CPU core and support modules
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tb_nexys2.vhd
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1-- $Id: tb_nexys2.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys2 - sim
7-- Description: Test bench for nexys2 (base)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/dcm_sfs
13-- tb_nexys2_core
14-- nexys2_aif [UUT]
15-- serport/tb/serport_master_tb
16--
17-- To test: generic, any nexys2_aif target
18--
19-- Target Devices: generic
20-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.33
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2016-09-02 805 3.2.3 tbcore_rlink without CLK_STOP now
25-- 2016-02-13 730 3.2.2 direct instantiation of tbcore_rlink
26-- 2016-01-03 724 3.2.1 use serport/tb/serport_master_tb
27-- 2015-04-12 666 3.2 use serport_master instead of serport_uart_rxtx
28-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
29-- 2011-11-26 433 3.0.2 remove O_FLA_CE_N from tb_nexys2_core
30-- 2011-11-21 432 3.0.1 now numeric_std clean; update O_FLA_CE_N usage
31-- 2010-12-30 351 3.0 use rlink/tb now
32-- 2010-11-13 338 1.0.3 now dcm aware: add O_CLKSYS, use rritb_core_dcm
33-- 2010-11-06 336 1.0.2 rename input pin CLK -> I_CLK50
34-- 2010-05-28 295 1.0.1 use serport_uart_rxtx
35-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board)
36------------------------------------------------------------------------------
37
38library ieee;
39use ieee.std_logic_1164.all;
40use ieee.numeric_std.all;
41use ieee.std_logic_textio.all;
42use std.textio.all;
43
44use work.slvtypes.all;
45use work.rlinklib.all;
46use work.xlib.all;
47use work.nexys2lib.all;
48use work.simlib.all;
49use work.simbus.all;
50use work.sys_conf.all;
51
52entity tb_nexys2 is
53end tb_nexys2;
54
55architecture sim of tb_nexys2 is
56
57 signal CLKOSC : slbit := '0';
58 signal CLKCOM : slbit := '0';
59
60 signal CLKCOM_CYCLE : integer := 0;
61
62 signal RESET : slbit := '0';
63 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
64 signal RXDATA : slv8 := (others=>'0');
65 signal RXVAL : slbit := '0';
66 signal RXERR : slbit := '0';
67 signal RXACT : slbit := '0';
68 signal TXDATA : slv8 := (others=>'0');
69 signal TXENA : slbit := '0';
70 signal TXBUSY : slbit := '0';
71
72 signal I_RXD : slbit := '1';
73 signal O_TXD : slbit := '1';
74 signal I_SWI : slv8 := (others=>'0');
75 signal I_BTN : slv4 := (others=>'0');
76 signal O_LED : slv8 := (others=>'0');
77 signal O_ANO_N : slv4 := (others=>'0');
78 signal O_SEG_N : slv8 := (others=>'0');
79 signal O_MEM_CE_N : slbit := '1';
80 signal O_MEM_BE_N : slv2 := (others=>'1');
81 signal O_MEM_WE_N : slbit := '1';
82 signal O_MEM_OE_N : slbit := '1';
83 signal O_MEM_ADV_N : slbit := '1';
84 signal O_MEM_CLK : slbit := '0';
85 signal O_MEM_CRE : slbit := '0';
86 signal I_MEM_WAIT : slbit := '0';
87 signal O_MEM_ADDR : slv23 := (others=>'Z');
88 signal IO_MEM_DATA : slv16 := (others=>'0');
89 signal O_FLA_CE_N : slbit := '0';
90
91 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
92
93 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
94
95 constant clock_period : Delay_length := 20 ns;
96 constant clock_offset : Delay_length := 200 ns;
97
98begin
99
100 CLKGEN : simclk
101 generic map (
104 port map (
105 CLK => CLKOSC
106 );
107
108 DCM_COM : dcm_sfs
109 generic map (
110 CLKFX_DIVIDE => sys_conf_clkfx_divide,
111 CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
112 CLKIN_PERIOD => 10.0)
113 port map (
114 CLKIN => CLKOSC,
115 CLKFX => CLKCOM,
116 LOCKED => open
117 );
118
119 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
120
121 TBCORE : entity work.tbcore_rlink
122 port map (
123 CLK => CLKCOM,
124 RX_DATA => TXDATA,
125 RX_VAL => TXENA,
126 RX_HOLD => TXBUSY,
127 TX_DATA => RXDATA,
128 TX_ENA => RXVAL
129 );
130
131 N2CORE : entity work.tb_nexys2_core
132 port map (
133 I_SWI => I_SWI,
134 I_BTN => I_BTN,
145 );
146
147 UUT : nexys2_aif
148 port map (
149 I_CLK50 => CLKOSC,
150 I_RXD => I_RXD,
151 O_TXD => O_TXD,
152 I_SWI => I_SWI,
153 I_BTN => I_BTN,
154 O_LED => O_LED,
155 O_ANO_N => O_ANO_N,
156 O_SEG_N => O_SEG_N,
157 O_MEM_CE_N => O_MEM_CE_N,
158 O_MEM_BE_N => O_MEM_BE_N,
159 O_MEM_WE_N => O_MEM_WE_N,
160 O_MEM_OE_N => O_MEM_OE_N,
161 O_MEM_ADV_N => O_MEM_ADV_N,
162 O_MEM_CLK => O_MEM_CLK,
163 O_MEM_CRE => O_MEM_CRE,
164 I_MEM_WAIT => I_MEM_WAIT,
165 O_MEM_ADDR => O_MEM_ADDR,
166 IO_MEM_DATA => IO_MEM_DATA,
167 O_FLA_CE_N => O_FLA_CE_N
168 );
169
170 SERMSTR : entity work.serport_master_tb
171 generic map (
172 CDWIDTH => CLKDIV'length)
173 port map (
174 CLK => CLKCOM,
175 RESET => RESET,
176 CLKDIV => CLKDIV,
178 ENAESC => '0',
179 RXDATA => RXDATA,
180 RXVAL => RXVAL,
181 RXERR => RXERR,
182 RXOK => '1',
183 TXDATA => TXDATA,
184 TXENA => TXENA,
185 TXBUSY => TXBUSY,
186 RXSD => O_TXD,
187 TXSD => I_RXD,
188 RXRTS_N => open,
189 TXCTS_N => '0'
190 );
191
192 proc_moni: process
193 variable oline : line;
194 begin
195
196 loop
197 wait until rising_edge(CLKCOM);
198
199 if RXERR = '1' then
200 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
201 writeline(output, oline);
202 end if;
203
204 end loop;
205
206 end process proc_moni;
207
208 proc_simbus: process (SB_VAL)
209 begin
210 if SB_VAL'event and to_x01(SB_VAL)='1' then
211 if SB_ADDR = sbaddr_portsel then
212 R_PORTSEL_XON <= to_x01(SB_DATA(1));
213 end if;
214 end if;
215 end process proc_simbus;
216
217end sim;
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' RXERR
Definition: tb_nexys2.vhd:66
slbit := '0' RESET
Definition: tb_nexys2.vhd:62
slv8 :=( others => '0') O_SEG_N
Definition: tb_nexys2.vhd:78
integer := 0 CLKCOM_CYCLE
Definition: tb_nexys2.vhd:60
slbit := '1' O_MEM_CE_N
Definition: tb_nexys2.vhd:79
slv2 := "00" CLKDIV
Definition: tb_nexys2.vhd:63
slv4 :=( others => '0') I_BTN
Definition: tb_nexys2.vhd:75
slbit := '0' TXENA
Definition: tb_nexys2.vhd:69
slv8 :=( others => '0') RXDATA
Definition: tb_nexys2.vhd:64
slv2 :=( others => '1') O_MEM_BE_N
Definition: tb_nexys2.vhd:80
Delay_length := 200 ns clock_offset
Definition: tb_nexys2.vhd:96
slv16 :=( others => '0') IO_MEM_DATA
Definition: tb_nexys2.vhd:88
slv8 :=( others => '0') O_LED
Definition: tb_nexys2.vhd:76
slbit := '0' O_FLA_CE_N
Definition: tb_nexys2.vhd:89
slbit := '0' RXACT
Definition: tb_nexys2.vhd:67
slv23 :=( others => 'Z') O_MEM_ADDR
Definition: tb_nexys2.vhd:87
slbit := '0' O_MEM_CRE
Definition: tb_nexys2.vhd:85
slbit := '0' RXVAL
Definition: tb_nexys2.vhd:65
slbit := '1' O_MEM_ADV_N
Definition: tb_nexys2.vhd:83
slbit := '1' O_TXD
Definition: tb_nexys2.vhd:73
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
Definition: tb_nexys2.vhd:93
slbit := '0' CLKOSC
Definition: tb_nexys2.vhd:57
slbit := '0' O_MEM_CLK
Definition: tb_nexys2.vhd:84
slbit := '1' O_MEM_OE_N
Definition: tb_nexys2.vhd:82
slv8 :=( others => '0') I_SWI
Definition: tb_nexys2.vhd:74
slbit := '0' CLKCOM
Definition: tb_nexys2.vhd:58
slbit := '0' I_MEM_WAIT
Definition: tb_nexys2.vhd:86
slbit := '0' TXBUSY
Definition: tb_nexys2.vhd:70
slv4 :=( others => '0') O_ANO_N
Definition: tb_nexys2.vhd:77
slbit := '0' R_PORTSEL_XON
Definition: tb_nexys2.vhd:91
slbit := '1' O_MEM_WE_N
Definition: tb_nexys2.vhd:81
slv8 :=( others => '0') TXDATA
Definition: tb_nexys2.vhd:68
Delay_length := 20 ns clock_period
Definition: tb_nexys2.vhd:95
slbit := '1' I_RXD
Definition: tb_nexys2.vhd:72
in O_MEM_WE_N slbit
in O_MEM_ADV_N slbit
out I_MEM_WAIT slbit
in O_MEM_CLK slbit
in O_MEM_OE_N slbit
in O_MEM_ADDR slv23
in O_MEM_CRE slbit
in O_MEM_CE_N slbit
inout IO_MEM_DATA slv16
in O_MEM_BE_N slv2
Definition: xlib.vhd:35