39use ieee.std_logic_1164.
all;
40use ieee.numeric_std.
all;
41use ieee.std_logic_textio.
all;
193 variable oline : line;
197 wait until rising_edge(CLKCOM);
201 writeline(output, oline);
206 end process proc_moni;
208 proc_simbus:
process (SB_VAL)
210 if SB_VAL'event and to_x01(SB_VAL)='1' then
215 end process proc_simbus;
CLKFX_DIVIDE positive := 1
CLKFX_MULTIPLY positive := 1
CLKIN_PERIOD real := 20.0
in CLKDIV slv( CDWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
slv4 :=( others => '0') I_BTN
slv8 :=( others => '0') RXDATA
slv2 :=( others => '1') O_MEM_BE_N
Delay_length := 200 ns clock_offset
slv16 :=( others => '0') IO_MEM_DATA
slv8 :=( others => '0') O_LED
slv23 :=( others => 'Z') O_MEM_ADDR
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TXDATA
Delay_length := 20 ns clock_period