34use ieee.std_logic_1164.
all;
35use ieee.numeric_std.
all;
36use ieee.std_logic_textio.
all;
178 UUT : nexys2_fusp_cuff_aif
274 end process proc_fx2_mux;
294 end process proc_ser_mux;
297 variable oline : line;
301 wait until rising_edge(CLKCOM);
304 writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
305 writeline(output, oline);
310 end process proc_moni;
312 proc_simbus:
process (SB_VAL)
314 if SB_VAL'event and to_x01(SB_VAL)='1' then
321 end process proc_simbus;
CLKFX_DIVIDE positive := 1
CLKFX_MULTIPLY positive := 1
CLKIN_PERIOD real := 20.0
in CLKDIV slv( CDWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv2 :=( others => '0') O_FX2_FIFO
slbit := '0' R_PORTSEL_FX2
slv8 :=( others => 'Z') IO_FX2_DATA
slv8 :=( others => '0') UART_TXDATA
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
slv8 :=( others => '0') FX2_TXDATA
slv4 :=( others => '0') I_FX2_FLAG
slbit := '1' O_FX2_SLWR_N
slv8 :=( others => '0') FX2_RXDATA
slbit := '1' O_FX2_SLRD_N
slv4 :=( others => '0') I_BTN
slbit := '1' O_FX2_PKTEND_N
slv2 :=( others => '1') O_MEM_BE_N
Delay_length := 200 ns clock_offset
slv16 :=( others => '0') IO_MEM_DATA
slbit := '1' O_FX2_SLOE_N
slv8 :=( others => '0') O_LED
slbit := '0' R_PORTSEL_SER
slv23 :=( others => 'Z') O_MEM_ADDR
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv8 :=( others => '0') TBC_TXDATA
slv8 :=( others => '0') UART_RXDATA
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slbit := '0' R_PORTSEL_XON
slbit := '0' O_FUSP_RTS_N
slv8 :=( others => '0') TBC_RXDATA
Delay_length := 20 ns clock_period
slbit := '0' I_FUSP_CTS_N