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W11 CPU core and support modules
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tb_nexys2_fusp_cuff.vhd
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1-- $Id: tb_nexys2_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys2_fusp_cuff - sim
7-- Description: Test bench for nexys2 (base+fusp+cuff)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- xlib/dcm_sfs
12-- rlink/tbcore/tbcore_rlink_dcm
13-- tb_nexys2_core
14-- serport/tb/serport_master_tb
15-- fx2lib/tb/fx2_2fifo_core
16-- nexys2_fusp_cuff_aif [UUT]
17--
18-- To test: generic, any nexys2_fusp_cuff_aif target
19--
20-- Target Devices: generic
21-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
22--
23-- Revision History:
24-- Date Rev Version Comment
25-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
26-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
27-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
28-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
29-- 2013-01-03 469 1.1 add fx2 model and data path
30-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
31------------------------------------------------------------------------------
32
33library ieee;
34use ieee.std_logic_1164.all;
35use ieee.numeric_std.all;
36use ieee.std_logic_textio.all;
37use std.textio.all;
38
39use work.slvtypes.all;
40use work.rlinklib.all;
41use work.xlib.all;
42use work.nexys2lib.all;
43use work.simlib.all;
44use work.simbus.all;
45use work.sys_conf.all;
46
49
50architecture sim of tb_nexys2_fusp_cuff is
51
52 signal CLKOSC : slbit := '0';
53 signal CLKCOM : slbit := '0';
54
55 signal CLKCOM_CYCLE : integer := 0;
56
57 signal RESET : slbit := '0';
58 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
59
60 signal TBC_RXDATA : slv8 := (others=>'0');
61 signal TBC_RXVAL : slbit := '0';
62 signal TBC_RXHOLD : slbit := '0';
63 signal TBC_TXDATA : slv8 := (others=>'0');
64 signal TBC_TXENA : slbit := '0';
65
66 signal UART_RXDATA : slv8 := (others=>'0');
67 signal UART_RXVAL : slbit := '0';
68 signal UART_RXERR : slbit := '0';
69 signal UART_RXACT : slbit := '0';
70 signal UART_TXDATA : slv8 := (others=>'0');
71 signal UART_TXENA : slbit := '0';
72 signal UART_TXBUSY : slbit := '0';
73
74 signal FX2_RXDATA : slv8 := (others=>'0');
75 signal FX2_RXENA : slbit := '0';
76 signal FX2_RXBUSY : slbit := '0';
77 signal FX2_TXDATA : slv8 := (others=>'0');
78 signal FX2_TXVAL : slbit := '0';
79
80 signal I_RXD : slbit := '1';
81 signal O_TXD : slbit := '1';
82 signal I_SWI : slv8 := (others=>'0');
83 signal I_BTN : slv4 := (others=>'0');
84 signal O_LED : slv8 := (others=>'0');
85 signal O_ANO_N : slv4 := (others=>'0');
86 signal O_SEG_N : slv8 := (others=>'0');
87
88 signal O_MEM_CE_N : slbit := '1';
89 signal O_MEM_BE_N : slv2 := (others=>'1');
90 signal O_MEM_WE_N : slbit := '1';
91 signal O_MEM_OE_N : slbit := '1';
92 signal O_MEM_ADV_N : slbit := '1';
93 signal O_MEM_CLK : slbit := '0';
94 signal O_MEM_CRE : slbit := '0';
95 signal I_MEM_WAIT : slbit := '0';
96 signal O_MEM_ADDR : slv23 := (others=>'Z');
97 signal IO_MEM_DATA : slv16 := (others=>'0');
98 signal O_FLA_CE_N : slbit := '0';
99
100 signal O_FUSP_RTS_N : slbit := '0';
101 signal I_FUSP_CTS_N : slbit := '0';
102 signal I_FUSP_RXD : slbit := '1';
103 signal O_FUSP_TXD : slbit := '1';
104
105 signal I_FX2_IFCLK : slbit := '0';
106 signal O_FX2_FIFO : slv2 := (others=>'0');
107 signal I_FX2_FLAG : slv4 := (others=>'0');
108 signal O_FX2_SLRD_N : slbit := '1';
109 signal O_FX2_SLWR_N : slbit := '1';
110 signal O_FX2_SLOE_N : slbit := '1';
111 signal O_FX2_PKTEND_N : slbit := '1';
112 signal IO_FX2_DATA : slv8 := (others=>'Z');
113
114 signal UART_RESET : slbit := '0';
115 signal UART_RXD : slbit := '1';
116 signal UART_TXD : slbit := '1';
117 signal CTS_N : slbit := '0';
118 signal RTS_N : slbit := '0';
119
120 signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
121 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
122 signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
123
124 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
125
126 constant clock_period : Delay_length := 20 ns;
127 constant clock_offset : Delay_length := 200 ns;
128
129begin
130
131 CLKGEN : simclk
132 generic map (
135 port map (
136 CLK => CLKOSC
137 );
138
139 DCM_COM : dcm_sfs
140 generic map (
141 CLKFX_DIVIDE => sys_conf_clkfx_divide,
142 CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
143 CLKIN_PERIOD => 20.0)
144 port map (
145 CLKIN => CLKOSC,
146 CLKFX => CLKCOM,
147 LOCKED => open
148 );
149
150 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
151
152 TBCORE : entity work.tbcore_rlink
153 port map (
154 CLK => CLKCOM,
156 RX_VAL => TBC_RXVAL,
160 );
161
162 N2CORE : entity work.tb_nexys2_core
163 port map (
164 I_SWI => I_SWI,
165 I_BTN => I_BTN,
176 );
177
178 UUT : nexys2_fusp_cuff_aif
179 port map (
180 I_CLK50 => CLKOSC,
181 I_RXD => I_RXD,
182 O_TXD => O_TXD,
183 I_SWI => I_SWI,
184 I_BTN => I_BTN,
185 O_LED => O_LED,
186 O_ANO_N => O_ANO_N,
187 O_SEG_N => O_SEG_N,
188 O_MEM_CE_N => O_MEM_CE_N,
189 O_MEM_BE_N => O_MEM_BE_N,
190 O_MEM_WE_N => O_MEM_WE_N,
191 O_MEM_OE_N => O_MEM_OE_N,
192 O_MEM_ADV_N => O_MEM_ADV_N,
193 O_MEM_CLK => O_MEM_CLK,
194 O_MEM_CRE => O_MEM_CRE,
195 I_MEM_WAIT => I_MEM_WAIT,
196 O_MEM_ADDR => O_MEM_ADDR,
197 IO_MEM_DATA => IO_MEM_DATA,
198 O_FLA_CE_N => O_FLA_CE_N,
199 O_FUSP_RTS_N => O_FUSP_RTS_N,
200 I_FUSP_CTS_N => I_FUSP_CTS_N,
201 I_FUSP_RXD => I_FUSP_RXD,
202 O_FUSP_TXD => O_FUSP_TXD,
203 I_FX2_IFCLK => I_FX2_IFCLK,
204 O_FX2_FIFO => O_FX2_FIFO,
205 I_FX2_FLAG => I_FX2_FLAG,
206 O_FX2_SLRD_N => O_FX2_SLRD_N,
207 O_FX2_SLWR_N => O_FX2_SLWR_N,
208 O_FX2_SLOE_N => O_FX2_SLOE_N,
209 O_FX2_PKTEND_N => O_FX2_PKTEND_N,
210 IO_FX2_DATA => IO_FX2_DATA
211 );
212
213 SERMSTR : entity work.serport_master_tb
214 generic map (
215 CDWIDTH => CLKDIV'length)
216 port map (
217 CLK => CLKCOM,
218 RESET => UART_RESET,
219 CLKDIV => CLKDIV,
221 ENAESC => '0',
223 RXVAL => UART_RXVAL,
224 RXERR => UART_RXERR,
225 RXOK => '1',
227 TXENA => UART_TXENA,
229 RXSD => UART_RXD,
230 TXSD => UART_TXD,
231 RXRTS_N => RTS_N,
232 TXCTS_N => CTS_N
233 );
234
235 FX2 : entity work.fx2_2fifo_core
236 port map (
237 CLK => CLKCOM,
238 RESET => '0',
240 RXENA => FX2_RXENA,
243 TXVAL => FX2_TXVAL,
245 FIFO => O_FX2_FIFO,
246 FLAG => I_FX2_FLAG,
252 );
253
254 proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
257 )
258 begin
259
260 if R_PORTSEL_FX2 = '0' then -- use serport
266 else -- otherwise use fx2
272 end if;
273
274 end process proc_fx2_mux;
275
276 proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
278 begin
279
280 if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
281 I_RXD <= UART_TXD; -- write port 0 inputs
282 UART_RXD <= O_TXD; -- get port 0 outputs
283 RTS_N <= '0';
284 I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
285 I_FUSP_CTS_N <= '0';
286 else -- otherwise use pmod1 rs232
287 I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
289 UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
291 I_RXD <= '1'; -- port 0 inputs to idle state
292 end if;
293
294 end process proc_ser_mux;
295
296 proc_moni: process
297 variable oline : line;
298 begin
299
300 loop
301 wait until rising_edge(CLKCOM);
302
303 if UART_RXERR = '1' then
304 writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
305 writeline(output, oline);
306 end if;
307
308 end loop;
309
310 end process proc_moni;
311
312 proc_simbus: process (SB_VAL)
313 begin
314 if SB_VAL'event and to_x01(SB_VAL)='1' then
315 if SB_ADDR = sbaddr_portsel then
316 R_PORTSEL_SER <= to_x01(SB_DATA(0));
317 R_PORTSEL_XON <= to_x01(SB_DATA(1));
318 R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
319 end if;
320 end if;
321 end process proc_simbus;
322
323end sim;
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
inout DATA slv8
in SLRD_N slbit
out RXBUSY slbit
out IFCLK slbit
out TXVAL slbit
out TXDATA slv8
in SLWR_N slbit
in SLOE_N slbit
in PKTEND_N slbit
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in O_MEM_WE_N slbit
in O_MEM_ADV_N slbit
out I_MEM_WAIT slbit
in O_MEM_CLK slbit
in O_MEM_OE_N slbit
in O_MEM_ADDR slv23
in O_MEM_CRE slbit
in O_MEM_CE_N slbit
inout IO_MEM_DATA slv16
in O_MEM_BE_N slv2
slv2 :=( others => '0') O_FX2_FIFO
slv8 :=( others => 'Z') IO_FX2_DATA
slv8 :=( others => '0') UART_TXDATA
slv8 :=( others => '0') O_SEG_N
slv8 :=( others => '0') FX2_TXDATA
slv4 :=( others => '0') I_FX2_FLAG
slv8 :=( others => '0') FX2_RXDATA
slv4 :=( others => '0') I_BTN
slv2 :=( others => '1') O_MEM_BE_N
Delay_length := 200 ns clock_offset
slv16 :=( others => '0') IO_MEM_DATA
slv8 :=( others => '0') O_LED
slv23 :=( others => 'Z') O_MEM_ADDR
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv8 :=( others => '0') TBC_TXDATA
slv8 :=( others => '0') UART_RXDATA
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slv8 :=( others => '0') TBC_RXDATA
Delay_length := 20 ns clock_period
Definition: xlib.vhd:35