w11 - vhd 0.794
W11 CPU core and support modules
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rbd_tst_rlink.vhd
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1-- $Id: rbd_tst_rlink.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rbd_tst_rlink - syn
7-- Description: rbus device for tst_rlink
8--
9-- Dependencies: rbus/rbd_tester
10-- rbus/rbd_bram
11-- rbus/rbd_rbmon
12-- rbus/rbd_eyemon
13-- rbus/rbd_timer
14-- rbus/rb_sres_or_3
15-- rbus/rb_sres_or_4
16--
17-- Test bench: nexys3/tb/tb_tst_rlink_n3
18--
19-- Target Devices: generic
20-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2014-11-09 603 4.0 use new rlink v4 iface and 4 bit STAT
25-- 2014-08-15 583 3.5 rb_mreq addr now 16 bit
26-- 2011-11-11 351 1.0 Initial version (derived from tst_rlink)
27------------------------------------------------------------------------------
28-- Usage of STAT signal:
29-- STAT(0): timer 0 busy
30-- STAT(1): timer 1 busy
31-- STAT(2:3): unused
32
33library ieee;
34use ieee.std_logic_1164.all;
35use ieee.numeric_std.all;
36
37use work.slvtypes.all;
38use work.rblib.all;
39use work.rbdlib.all;
40
41-- ----------------------------------------------------------------------------
42
43entity rbd_tst_rlink is -- rbus device for tst_rlink
44 port (
45 CLK : in slbit; -- clock
46 RESET : in slbit; -- reset
47 CE_USEC : in slbit; -- usec pulse
48 RB_MREQ : in rb_mreq_type; -- rbus: request
49 RB_SRES : out rb_sres_type; -- rbus: response
50 RB_LAM : out slv16; -- rbus: look at me
51 RB_STAT : out slv4; -- rbus: status flags
52 RB_SRES_TOP : in rb_sres_type; -- top-level rb_sres, for rbd_mon
53 RXSD : in slbit; -- serport rxsd, for rbd_eyemon
54 RXACT : in slbit; -- serport rxact, for rbd_eyemon
55 STAT : out slv8 -- status flags
56
57 );
59
60architecture syn of rbd_tst_rlink is
61
62 signal RB_SRES_TEST : rb_sres_type := rb_sres_init;
63 signal RB_SRES_BRAM : rb_sres_type := rb_sres_init;
64 signal RB_SRES_MON : rb_sres_type := rb_sres_init;
65 signal RB_SRES_EMON : rb_sres_type := rb_sres_init;
66 signal RB_SRES_TIM0 : rb_sres_type := rb_sres_init;
67 signal RB_SRES_TIM1 : rb_sres_type := rb_sres_init;
68 signal RB_SRES_SUM1 : rb_sres_type := rb_sres_init;
69
70 signal RB_LAM_TEST : slv16 := (others=>'0');
71
72 signal TIM0_DONE : slbit := '0';
73 signal TIM0_BUSY : slbit := '0';
74 signal TIM1_DONE : slbit := '0';
75 signal TIM1_BUSY : slbit := '0';
76
77 -- rbaddr_rbmon -- default addr - ffe8/8: 1111 1111 1110 1xxx
78 -- rbaddr_tester -- default addr - ffe0/8: 1111 1111 1110 0xxx
79 constant rbaddr_eyemon : slv16 := x"ffd0"; -- ffd0/4: 1111 1111 1101 00xx
80 constant rbaddr_tim1 : slv16 := x"fe11"; -- fe11/1: 1111 1110 0001 0001
81 constant rbaddr_tim0 : slv16 := x"fe10"; -- fe10/1: 1111 1110 0001 0000
82 constant rbaddr_bram : slv16 := x"fe00"; -- fe00/2: 1111 1110 0000 00xx
83
84begin
85
86 TEST : rbd_tester
87 generic map (
88 RB_ADDR => rbaddr_tester)
89 port map (
90 CLK => CLK,
91 RESET => RESET,
96 );
97
98 BRAM : rbd_bram
99 generic map (
101 port map (
102 CLK => CLK,
103 RESET => RESET,
104 RB_MREQ => RB_MREQ,
106 );
107
108 MON : rbd_rbmon
109 generic map (
110 RB_ADDR => rbaddr_rbmon,
111 AWIDTH => 9)
112 port map (
113 CLK => CLK,
114 RESET => RESET,
115 RB_MREQ => RB_MREQ,
118 );
119
120 EMON : rbd_eyemon
121 generic map (
123 RDIV => slv(to_unsigned(0,8)))
124 port map (
125 CLK => CLK,
126 RESET => RESET,
127 RB_MREQ => RB_MREQ,
129 RXSD => RXSD,
130 RXACT => RXACT
131 );
132
133 TIM0 : rbd_timer
134 generic map (
136 port map (
137 CLK => CLK,
138 CE_USEC => CE_USEC,
139 RESET => RESET,
140 RB_MREQ => RB_MREQ,
142 DONE => TIM0_DONE,
143 BUSY => TIM0_BUSY
144 );
145
146 TIM1 : rbd_timer
147 generic map (
149 port map (
150 CLK => CLK,
151 CE_USEC => CE_USEC,
152 RESET => RESET,
153 RB_MREQ => RB_MREQ,
155 DONE => TIM1_DONE,
156 BUSY => TIM1_BUSY
157 );
158
159 RB_SRES_OR1 : rb_sres_or_3
160 port map (
165 );
166
167 RB_SRES_OR : rb_sres_or_4
168 port map (
174 );
175
176 RB_LAM(15 downto 2) <= RB_LAM_TEST(15 downto 2);
177 RB_LAM(1) <= TIM1_DONE;
178 RB_LAM(0) <= TIM0_DONE;
179
180 STAT(0) <= TIM0_BUSY;
181 STAT(1) <= TIM1_BUSY;
182 STAT(7 downto 2) <= (others=>'0');
183
184end syn;
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_2 rb_sres_type := rb_sres_init
in RB_SRES_3 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_4 rb_sres_type := rb_sres_init
in RESET slbit
Definition: rbd_bram.vhd:53
in CLK slbit
Definition: rbd_bram.vhd:52
in RB_MREQ rb_mreq_type
Definition: rbd_bram.vhd:54
RB_ADDR slv16 :=( others => '0')
Definition: rbd_bram.vhd:50
out RB_SRES rb_sres_type
Definition: rbd_bram.vhd:56
in RESET slbit
Definition: rbd_eyemon.vhd:66
in RXSD slbit
Definition: rbd_eyemon.vhd:69
in CLK slbit
Definition: rbd_eyemon.vhd:65
in RXACT slbit
Definition: rbd_eyemon.vhd:71
in RB_MREQ rb_mreq_type
Definition: rbd_eyemon.vhd:67
RB_ADDR slv16 :=( others => '0')
Definition: rbd_eyemon.vhd:62
RDIV slv8 :=( others => '0')
Definition: rbd_eyemon.vhd:63
out RB_SRES rb_sres_type
Definition: rbd_eyemon.vhd:68
in RESET slbit
Definition: rbd_rbmon.vhd:98
RB_ADDR slv16 := rbaddr_rbmon
Definition: rbd_rbmon.vhd:94
AWIDTH natural := 9
Definition: rbd_rbmon.vhd:95
in CLK slbit
Definition: rbd_rbmon.vhd:97
in RB_MREQ rb_mreq_type
Definition: rbd_rbmon.vhd:99
out RB_SRES rb_sres_type
Definition: rbd_rbmon.vhd:100
in RB_SRES_SUM rb_sres_type
Definition: rbd_rbmon.vhd:102
in RESET slbit
Definition: rbd_tester.vhd:66
RB_ADDR slv16 := rbaddr_tester
Definition: rbd_tester.vhd:63
out RB_STAT slv4
Definition: rbd_tester.vhd:71
out RB_LAM slv16
Definition: rbd_tester.vhd:69
in CLK slbit
Definition: rbd_tester.vhd:65
in RB_MREQ rb_mreq_type
Definition: rbd_tester.vhd:67
out RB_SRES rb_sres_type
Definition: rbd_tester.vhd:68
in RESET slbit
Definition: rbd_timer.vhd:47
in CE_USEC slbit
Definition: rbd_timer.vhd:46
out BUSY slbit
Definition: rbd_timer.vhd:52
out DONE slbit
Definition: rbd_timer.vhd:50
in CLK slbit
Definition: rbd_timer.vhd:45
in RB_MREQ rb_mreq_type
Definition: rbd_timer.vhd:48
RB_ADDR slv16 :=( others => '0')
Definition: rbd_timer.vhd:43
out RB_SRES rb_sres_type
Definition: rbd_timer.vhd:49
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31