w11 - vhd 0.794
W11 CPU core and support modules
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rgbdrv_analog_rbus.vhd
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1-- $Id: rgbdrv_analog_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2016-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rgbdrv_analog_rbus - syn
7-- Description: rgb analog from rbus
8--
9-- Dependencies: bpgen/rgbdrv_analog
10--
11-- Test bench: -
12--
13-- Target Devices: generic
14-- Tool versions: ise 14.7; viv 2015.4-2016.4; ghdl 0.31-0.34
15--
16-- Revision History:
17-- Date Rev Version Comment
18-- 2017-06-05 907 1.1 add ACTLOW generic to invert output polarity
19-- 2016-02-20 724 1.0 Initial version
20------------------------------------------------------------------------------
21--
22-- rbus registers:
23--
24-- Addr Bits Name r/w/f Function
25-- 00 red r/w/- red channel
26-- 01 green r/w/- green channel
27-- 10 blue r/w/- blue channel
28--
29
30library ieee;
31use ieee.std_logic_1164.all;
32use ieee.numeric_std.all;
33
34use work.slvtypes.all;
35use work.rblib.all;
36use work.bpgenlib.all;
37
38-- ----------------------------------------------------------------------------
39
40entity rgbdrv_analog_rbus is -- rgb analog from rbus
41 generic (
42 DWIDTH : positive := 8; -- dimmer width
43 ACTLOW : slbit := '0'; -- invert output polarity
44 RB_ADDR : slv16 := x"0000");
45 port (
46 CLK : in slbit; -- clock
47 RESET : in slbit := '0'; -- reset
48 RB_MREQ : in rb_mreq_type; -- rbus: request
49 RB_SRES : out rb_sres_type; -- rbus: response
50 RGBCNTL : in slv3; -- rgb control
51 DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
52 O_RGBLED : out slv3 -- pad-o: rgb led
53 );
55
56architecture syn of rgbdrv_analog_rbus is
57
58 type regs_type is record
59 rbsel : slbit; -- rbus select
60 dimr : slv(DWIDTH-1 downto 0); -- dim red
61 dimg : slv(DWIDTH-1 downto 0); -- dim green
62 dimb : slv(DWIDTH-1 downto 0); -- dim blue
63 end record regs_type;
64
65 constant dimzero : slv(DWIDTH-1 downto 0) := (others=>'0');
66
67 constant regs_init : regs_type := (
68 '0', -- rbsel
69 dimzero, -- dimr
70 dimzero, -- dimg
71 dimzero -- dimb
72 );
73
74 signal R_REGS : regs_type := regs_init; -- state registers
75 signal N_REGS : regs_type := regs_init; -- next value state regs
76
77 subtype dim_rbf is integer range DWIDTH-1 downto 0;
78
79 constant rbaddr_dimr: slv2 := "00"; -- 0 r/w/-
80 constant rbaddr_dimg: slv2 := "01"; -- 1 r/w/-
81 constant rbaddr_dimb: slv2 := "10"; -- 2 r/w/-
82
83begin
84
85 assert DWIDTH<=16
86 report "assert (DWIDTH<=16)"
87 severity failure;
88
89 RGB : rgbdrv_analog
90 generic map (
91 DWIDTH => DWIDTH,
92 ACTLOW => ACTLOW)
93 port map (
94 CLK => CLK,
95 RESET => RESET,
98 DIMR => R_REGS.dimr,
99 DIMG => R_REGS.dimg,
100 DIMB => R_REGS.dimb,
102 );
103
104 proc_regs: process (CLK)
105 begin
106
107 if rising_edge(CLK) then
108 if RESET = '1' then
109 R_REGS <= regs_init;
110 else
111 R_REGS <= N_REGS;
112 end if;
113 end if;
114
115 end process proc_regs;
116
117 proc_next: process (R_REGS, RB_MREQ)
118
119 variable r : regs_type := regs_init;
120 variable n : regs_type := regs_init;
121
122 variable irb_ack : slbit := '0';
123 variable irb_busy : slbit := '0';
124 variable irb_err : slbit := '0';
125 variable irb_dout : slv16 := (others=>'0');
126 variable irbena : slbit := '0';
127
128 begin
129
130 r := R_REGS;
131 n := R_REGS;
132
133 irb_ack := '0';
134 irb_busy := '0';
135 irb_err := '0';
136 irb_dout := (others=>'0');
137
138 irbena := RB_MREQ.re or RB_MREQ.we;
139
140 -- rbus address decoder
141 n.rbsel := '0';
142 if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
143 n.rbsel := '1';
144 end if;
145
146 -- rbus transactions
147 if r.rbsel = '1' then
148 irb_ack := irbena; -- ack all accesses
149
150 case RB_MREQ.addr(1 downto 0) is
151
152 when rbaddr_dimr =>
153 irb_dout(dim_rbf) := r.dimr;
154 if RB_MREQ.we = '1' then
155 n.dimr := RB_MREQ.din(dim_rbf);
156 end if;
157
158 when rbaddr_dimg =>
159 irb_dout(dim_rbf) := r.dimg;
160 if RB_MREQ.we = '1' then
161 n.dimg := RB_MREQ.din(dim_rbf);
162 end if;
163
164 when rbaddr_dimb =>
165 irb_dout(dim_rbf) := r.dimb;
166 if RB_MREQ.we = '1' then
167 n.dimb := RB_MREQ.din(dim_rbf);
168 end if;
169
170 when others =>
171 irb_ack := '0';
172
173 end case;
174
175 end if;
176
177 N_REGS <= n;
178
179 RB_SRES <= rb_sres_init;
180 RB_SRES.ack <= irb_ack;
181 RB_SRES.busy <= irb_busy;
182 RB_SRES.err <= irb_err;
183 RB_SRES.dout <= irb_dout;
184
185 end process proc_next;
186
187end syn;
Definition: rblib.vhd:32
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
regs_type :=( '0', dimzero, dimzero, dimzero) regs_init
integer range DWIDTH- 1 downto 0 dim_rbf
slv( DWIDTH- 1 downto 0) :=( others => '0') dimzero
RB_ADDR slv16 := x"0000"
in DIMCNTL slv( DWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
in RGBCNTL slv3
DWIDTH positive := 8
out O_RGBLED slv3
in DIMB slv( DWIDTH- 1 downto 0)
in DIMCNTL slv( DWIDTH- 1 downto 0)
in DIMG slv( DWIDTH- 1 downto 0)
ACTLOW slbit := '0'
in CLK slbit
in DIMR slv( DWIDTH- 1 downto 0)
in RESET slbit := '0'
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31