31use ieee.std_logic_1164.
all;
32use ieee.numeric_std.
all;
86 report "assert (DWIDTH<=16)"
107 if rising_edge(CLK) then
115 end process proc_regs;
122 variable irb_ack : slbit := '0';
123 variable irb_busy : slbit := '0';
124 variable irb_err : slbit := '0';
125 variable irb_dout : slv16 := (others=>'0');
126 variable irbena : slbit := '0';
136 irb_dout := (others=>'0');
147 if r.rbsel = '1' then
150 case RB_MREQ.addr(1 downto 0) is
185 end process proc_next;
regs_type := regs_init N_REGS
regs_type := regs_init R_REGS
regs_type :=( '0', dimzero, dimzero, dimzero) regs_init
integer range DWIDTH- 1 downto 0 dim_rbf
slv( DWIDTH- 1 downto 0) :=( others => '0') dimzero
in DIMCNTL slv( DWIDTH- 1 downto 0)
in DIMB slv( DWIDTH- 1 downto 0)
in DIMCNTL slv( DWIDTH- 1 downto 0)
in DIMG slv( DWIDTH- 1 downto 0)
in DIMR slv( DWIDTH- 1 downto 0)
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 1 downto 0) slv2