w11 - vhd 0.794
W11 CPU core and support modules
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serport_1clock.vhd
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1-- $Id: serport_1clock.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: serport_1clock - syn
7-- Description: serial port: serial port module, 1 clock domain
8--
9-- Dependencies: serport_uart_rxtx_ab
10-- serport_xonrx
11-- serport_xontx
12-- memlib/fifo_1c_dram
13-- Test bench: -
14-- Target Devices: generic
15-- Tool versions: ise 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
16--
17-- Synthesized (xst):
18-- Date Rev ise Target flop lutl lutm slic t peri
19-- 2015-04-12 666 14.7 131013 xc6slx16-2 171 239 32 94 s 6.3
20-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
21--
22-- Revision History:
23-- Date Rev Version Comment
24-- 2015-04-11 666 1.1.1 add sim assertions for RXOVR and RXERR
25-- 2015-02-01 641 1.1 add CLKDIV_F for autobaud;
26-- 2011-12-10 438 1.0.2 internal reset on abact
27-- 2011-12-09 437 1.0.1 rename stat->moni port
28-- 2011-11-13 424 1.0 Initial version
29-- 2011-10-23 419 0.5 First draft
30------------------------------------------------------------------------------
31
32library ieee;
33use ieee.std_logic_1164.all;
34use ieee.numeric_std.all;
35
36use work.slvtypes.all;
37use work.serportlib.all;
38use work.memlib.all;
39
40entity serport_1clock is -- serial port module, 1 clock domain
41 generic (
42 CDWIDTH : positive := 13; -- clk divider width
43 CDINIT : natural := 15; -- clk divider initial/reset setting
44 RXFAWIDTH : natural := 5; -- rx fifo address width
45 TXFAWIDTH : natural := 5); -- tx fifo address width
46 port (
47 CLK : in slbit; -- clock
48 CE_MSEC : in slbit; -- 1 msec clock enable
49 RESET : in slbit; -- reset
50 ENAXON : in slbit; -- enable xon/xoff handling
51 ENAESC : in slbit; -- enable xon/xoff escaping
52 RXDATA : out slv8; -- receiver data out
53 RXVAL : out slbit; -- receiver data valid
54 RXHOLD : in slbit; -- receiver data hold
55 TXDATA : in slv8; -- transmit data in
56 TXENA : in slbit; -- transmit data enable
57 TXBUSY : out slbit; -- transmit busy
58 MONI : out serport_moni_type; -- serport monitor port
59 RXSD : in slbit; -- receive serial data (uart view)
60 TXSD : out slbit; -- transmit serial data (uart view)
61 RXRTS_N : out slbit; -- receive rts (uart view, act.low)
62 TXCTS_N : in slbit -- transmit cts (uart view, act.low)
63 );
65
66
67architecture syn of serport_1clock is
68
69 signal R_RXOK : slbit := '1';
70
71 signal RESET_INT : slbit := '0';
72
73 signal UART_RXDATA : slv8 := (others=>'0');
74 signal UART_RXVAL : slbit := '0';
75 signal UART_TXDATA : slv8 := (others=>'0');
76 signal UART_TXENA : slbit := '0';
77 signal UART_TXBUSY : slbit := '0';
78
79 signal XONTX_TXENA : slbit := '0';
80 signal XONTX_TXBUSY : slbit := '0';
81
82 signal RXFIFO_DI : slv8 := (others=>'0');
83 signal RXFIFO_ENA : slbit := '0';
84 signal RXFIFO_BUSY : slbit := '0';
85 signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
86 signal TXFIFO_DO : slv8 := (others=>'0');
87 signal TXFIFO_VAL : slbit := '0';
88 signal TXFIFO_HOLD : slbit := '0';
89
90 signal RXERR : slbit := '0';
91 signal RXOVR : slbit := '0';
92 signal RXACT : slbit := '0';
93 signal ABACT : slbit := '0';
94 signal ABDONE : slbit := '0';
95 signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
96 signal ABCLKDIV_F : slv3 := (others=>'0');
97
98 signal TXOK : slbit := '0';
99 signal RXOK : slbit := '0';
100
101begin
102
103 assert CDWIDTH<=16
104 report "assert(CDWIDTH<=16): max width of UART clock divider"
105 severity failure;
106
107 UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
108 generic map (
109 CDWIDTH => CDWIDTH,
110 CDINIT => CDINIT)
111 port map (
112 CLK => CLK,
113 CE_MSEC => CE_MSEC,
114 RESET => RESET,
115 RXSD => RXSD,
116 RXDATA => UART_RXDATA,
117 RXVAL => UART_RXVAL,
118 RXERR => RXERR,
119 RXACT => RXACT,
120 TXSD => TXSD,
121 TXDATA => UART_TXDATA,
122 TXENA => UART_TXENA,
123 TXBUSY => UART_TXBUSY,
124 ABACT => ABACT,
125 ABDONE => ABDONE,
126 ABCLKDIV => ABCLKDIV,
127 ABCLKDIV_F => ABCLKDIV_F
128 );
129
130 RESET_INT <= RESET or ABACT;
131
132 XONRX : serport_xonrx -- xon/xoff logic rx path
133 port map (
134 CLK => CLK,
135 RESET => RESET_INT,
136 ENAXON => ENAXON,
137 ENAESC => ENAESC,
138 UART_RXDATA => UART_RXDATA,
139 UART_RXVAL => UART_RXVAL,
140 RXDATA => RXFIFO_DI,
141 RXVAL => RXFIFO_ENA,
142 RXHOLD => RXFIFO_BUSY,
143 RXOVR => RXOVR,
144 TXOK => TXOK
145 );
146
147 XONTX : serport_xontx -- xon/xoff logic tx path
148 port map (
149 CLK => CLK,
150 RESET => RESET_INT,
151 ENAXON => ENAXON,
152 ENAESC => ENAESC,
153 UART_TXDATA => UART_TXDATA,
154 UART_TXENA => XONTX_TXENA,
155 UART_TXBUSY => XONTX_TXBUSY,
156 TXDATA => TXFIFO_DO,
157 TXENA => TXFIFO_VAL,
158 TXBUSY => TXFIFO_HOLD,
159 RXOK => RXOK,
160 TXOK => TXOK
161 );
162
163 RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
164 generic map (
165 AWIDTH => RXFAWIDTH,
166 DWIDTH => 8)
167 port map (
168 CLK => CLK,
169 RESET => RESET_INT,
170 DI => RXFIFO_DI,
171 ENA => RXFIFO_ENA,
172 BUSY => RXFIFO_BUSY,
173 DO => RXDATA,
174 VAL => RXVAL,
175 HOLD => RXHOLD,
176 SIZE => RXFIFO_SIZE
177 );
178
179 TXFIFO : fifo_1c_dram -- output fifo, 1 clock, dram based
180 generic map (
181 AWIDTH => TXFAWIDTH,
182 DWIDTH => 8)
183 port map (
184 CLK => CLK,
185 RESET => RESET_INT,
186 DI => TXDATA,
187 ENA => TXENA,
188 BUSY => TXBUSY,
189 DO => TXFIFO_DO,
190 VAL => TXFIFO_VAL,
191 HOLD => TXFIFO_HOLD,
192 SIZE => open
193 );
194
195 -- receive back pressure
196 -- on if fifo more than 3/4 full
197 -- off if fifo less than 1/2 full
198 proc_rxok: process (CLK)
199 constant rxsize_rxok_off: slv3 := "011";
200 constant rxsize_rxok_on: slv3 := "010";
201 variable rxsize_msb : slv3 := "000";
202 begin
203 if rising_edge(CLK) then
204 if RESET_INT = '1' then
205 R_RXOK <= '1';
206 else
207 rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
208 if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
209 R_RXOK <= '0';
210 elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
211 R_RXOK <= '1';
212 end if;
213 end if;
214 end if;
215 end process proc_rxok;
216
217 RXOK <= R_RXOK;
218 RXRTS_N <= not R_RXOK;
219
220 proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
221 begin
222 if TXCTS_N = '0' then -- transmit cts asserted
225 else -- transmit cts not asserted
226 UART_TXENA <= '0';
227 XONTX_TXBUSY <= '1';
228 end if;
229 end process proc_cts;
230
231 MONI.rxerr <= RXERR;
232 MONI.rxovr <= RXOVR;
233 MONI.rxact <= RXACT;
234 MONI.txact <= UART_TXBUSY;
235 MONI.abact <= ABACT;
236 MONI.abdone <= ABDONE;
237 MONI.rxok <= RXOK;
238 MONI.txok <= TXOK;
239
240 proc_abclkdiv: process (ABCLKDIV, ABCLKDIV_F)
241 begin
242 MONI.abclkdiv <= (others=>'0');
243 MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
244 MONI.abclkdiv_f <= ABCLKDIV_F;
245 end process proc_abclkdiv;
246
247-- synthesis translate_off
248
249 proc_check: process (CLK)
250 begin
251 if rising_edge(CLK) then
252 assert RXOVR = '0'
253 report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) &
254 "; data loss in receive fifo"
255 severity warning;
256 assert RXERR = '0'
257 report "serport_1clock-W: RXERR = " & slbit'image(RXERR) &
258 "; spurious receive error"
259 severity warning;
260 end if;
261 end process proc_check;
262
263-- synthesis translate_on
264
265end syn;
slbit := '0' RXERR
slbit := '0' TXFIFO_HOLD
slv8 :=( others => '0') UART_TXDATA
slbit := '0' RESET_INT
slbit := '1' R_RXOK
slbit := '0' XONTX_TXENA
slbit := '0' UART_RXVAL
slv3 :=( others => '0') ABCLKDIV_F
slbit := '0' RXFIFO_ENA
slv8 :=( others => '0') TXFIFO_DO
slbit := '0' XONTX_TXBUSY
slbit := '0' ABACT
slbit := '0' ABDONE
slbit := '0' RXOVR
slv( RXFAWIDTH downto 0) :=( others => '0') RXFIFO_SIZE
slbit := '0' RXACT
slbit := '0' RXFIFO_BUSY
slbit := '0' UART_TXENA
slv8 :=( others => '0') UART_RXDATA
slbit := '0' TXFIFO_VAL
slv( CDWIDTH- 1 downto 0) :=( others => '0') ABCLKDIV
slv8 :=( others => '0') RXFIFO_DI
slbit := '0' UART_TXBUSY
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
in CE_MSEC slbit
out TXBUSY slbit
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31