33use ieee.std_logic_1164.
all;
34use ieee.numeric_std.
all;
58 MONI : out serport_moni_type;
104 report "assert(CDWIDTH<=16): max width of UART clock divider"
163 RXFIFO :
fifo_1c_dram -- input fifo,
1 clock, dram based
179 TXFIFO :
fifo_1c_dram -- output fifo,
1 clock, dram based
199 constant rxsize_rxok_off
: slv3 := "011";
200 constant rxsize_rxok_on
: slv3 := "010";
201 variable rxsize_msb : slv3 := "000";
203 if rising_edge(CLK) then
208 if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
210 elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
215 end process proc_rxok;
229 end process proc_cts;
242 MONI.abclkdiv <= (others=>'0');
245 end process proc_abclkdiv;
251 if rising_edge(CLK) then
253 report "serport_1clock-W: RXOVR = " & slbit'image(RXOVR) &
254 "; data loss in receive fifo"
257 report "serport_1clock-W: RXERR = " & slbit'image(RXERR) &
258 "; spurious receive error"
261 end process proc_check;
slv8 :=( others => '0') UART_TXDATA
slv3 :=( others => '0') ABCLKDIV_F
slv8 :=( others => '0') TXFIFO_DO
slbit := '0' XONTX_TXBUSY
slv( RXFAWIDTH downto 0) :=( others => '0') RXFIFO_SIZE
slv8 :=( others => '0') UART_RXDATA
slv( CDWIDTH- 1 downto 0) :=( others => '0') ABCLKDIV
slv8 :=( others => '0') RXFIFO_DI
out MONI serport_moni_type
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 7 downto 0) slv8