29use ieee.std_logic_1164.
all;
30use ieee.numeric_std.
all;
31use ieee.std_logic_textio.
all;
77 GINIT : entity work.gsr_pulse;
148 variable oline : line;
152 wait until rising_edge(CLKCOM);
156 writeline(output, oline);
161 end process proc_moni;
169 proc_simbus:
process (SB_VAL)
171 if SB_VAL'event and to_x01(SB_VAL)='1' then
176 end process proc_simbus;
in CLKDIV slv( CDWIDTH- 1 downto 0)
VCO_MULTIPLY positive := 1
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
integer := 0 CLKCOM_CYCLE
Delay_length := 83.333 ns clock_period
slv8 :=( others => '0') RXDATA
Delay_length := 2000 ns clock_offset
slv2 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED0_N
slbit := '0' R_PORTSEL_XON
slv2 :=( others => '0') O_LED
slv8 :=( others => '0') TXDATA