w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
tb_nexys3_fusp_cuff.vhd
Go to the documentation of this file.
1-- $Id: tb_nexys3_fusp_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys3_fusp_cuff - sim
7-- Description: Test bench for nexys3 (base+fusp+cuff)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- xlib/s6_cmt_sfs
12-- rlink/tbcore/tbcore_rlink
13-- tb_nexys3_core
14-- serport/tb/serport_master_tb
15-- fx2lib/tb/fx2_2fifo_core
16-- nexys3_fusp_cuff_aif [UUT]
17--
18-- To test: generic, any nexys3_fusp_cuff_aif target
19--
20-- Target Devices: generic
21-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
22--
23-- Revision History:
24-- Date Rev Version Comment
25-- 2016-09-02 805 1.2.3 tbcore_rlink without CLK_STOP now
26-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
27-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
28-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
29-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
30-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
31-- tb_nexys2_fusp_cuff)
32------------------------------------------------------------------------------
33
34library ieee;
35use ieee.std_logic_1164.all;
36use ieee.numeric_std.all;
37use ieee.std_logic_textio.all;
38use std.textio.all;
39
40use work.slvtypes.all;
41use work.rlinklib.all;
42use work.xlib.all;
43use work.nexys3lib.all;
44use work.simlib.all;
45use work.simbus.all;
46use work.sys_conf.all;
47
50
51architecture sim of tb_nexys3_fusp_cuff is
52
53 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
54 signal CLKCOM : slbit := '0'; -- communication clock
55
56 signal CLKCOM_CYCLE : integer := 0;
57
58 signal RESET : slbit := '0';
59 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
60
61 signal TBC_RXDATA : slv8 := (others=>'0');
62 signal TBC_RXVAL : slbit := '0';
63 signal TBC_RXHOLD : slbit := '0';
64 signal TBC_TXDATA : slv8 := (others=>'0');
65 signal TBC_TXENA : slbit := '0';
66
67 signal UART_RXDATA : slv8 := (others=>'0');
68 signal UART_RXVAL : slbit := '0';
69 signal UART_RXERR : slbit := '0';
70 signal UART_TXDATA : slv8 := (others=>'0');
71 signal UART_TXENA : slbit := '0';
72 signal UART_TXBUSY : slbit := '0';
73
74 signal FX2_RXDATA : slv8 := (others=>'0');
75 signal FX2_RXENA : slbit := '0';
76 signal FX2_RXBUSY : slbit := '0';
77 signal FX2_TXDATA : slv8 := (others=>'0');
78 signal FX2_TXVAL : slbit := '0';
79
80 signal I_RXD : slbit := '1';
81 signal O_TXD : slbit := '1';
82 signal I_SWI : slv8 := (others=>'0');
83 signal I_BTN : slv5 := (others=>'0');
84 signal O_LED : slv8 := (others=>'0');
85 signal O_ANO_N : slv4 := (others=>'0');
86 signal O_SEG_N : slv8 := (others=>'0');
87
88 signal O_MEM_CE_N : slbit := '1';
89 signal O_MEM_BE_N : slv2 := (others=>'1');
90 signal O_MEM_WE_N : slbit := '1';
91 signal O_MEM_OE_N : slbit := '1';
92 signal O_MEM_ADV_N : slbit := '1';
93 signal O_MEM_CLK : slbit := '0';
94 signal O_MEM_CRE : slbit := '0';
95 signal I_MEM_WAIT : slbit := '0';
96 signal O_MEM_ADDR : slv23 := (others=>'Z');
97 signal IO_MEM_DATA : slv16 := (others=>'0');
98 signal O_PPCM_CE_N : slbit := '0';
99 signal O_PPCM_RST_N : slbit := '0';
100
101 signal O_FUSP_RTS_N : slbit := '0';
102 signal I_FUSP_CTS_N : slbit := '0';
103 signal I_FUSP_RXD : slbit := '1';
104 signal O_FUSP_TXD : slbit := '1';
105
106 signal I_FX2_IFCLK : slbit := '0';
107 signal O_FX2_FIFO : slv2 := (others=>'0');
108 signal I_FX2_FLAG : slv4 := (others=>'0');
109 signal O_FX2_SLRD_N : slbit := '1';
110 signal O_FX2_SLWR_N : slbit := '1';
111 signal O_FX2_SLOE_N : slbit := '1';
112 signal O_FX2_PKTEND_N : slbit := '1';
113 signal IO_FX2_DATA : slv8 := (others=>'Z');
114
115 signal UART_RESET : slbit := '0';
116 signal UART_RXD : slbit := '1';
117 signal UART_TXD : slbit := '1';
118 signal CTS_N : slbit := '0';
119 signal RTS_N : slbit := '0';
120
121 signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
122 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
123 signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
124
125 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
126
127 constant clock_period : Delay_length := 10 ns;
128 constant clock_offset : Delay_length := 200 ns;
129
130begin
131
132 CLKGEN : simclk
133 generic map (
136 port map (
137 CLK => CLKOSC
138 );
139
140 CLKGEN_COM : s6_cmt_sfs
141 generic map (
142 VCO_DIVIDE => sys_conf_clksys_vcodivide,
143 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
144 OUT_DIVIDE => sys_conf_clksys_outdivide,
145 CLKIN_PERIOD => 10.0,
146 CLKIN_JITTER => 0.01,
147 STARTUP_WAIT => false,
148 GEN_TYPE => sys_conf_clksys_gentype)
149 port map (
150 CLKIN => CLKOSC,
151 CLKFX => CLKCOM,
152 LOCKED => open
153 );
154
155 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
156
157 TBCORE : entity work.tbcore_rlink
158 port map (
159 CLK => CLKCOM,
161 RX_VAL => TBC_RXVAL,
165 );
166
167 N3CORE : entity work.tb_nexys3_core
168 port map (
169 I_SWI => I_SWI,
170 I_BTN => I_BTN,
181 );
182
183 UUT : nexys3_fusp_cuff_aif
184 port map (
185 I_CLK100 => CLKOSC,
186 I_RXD => I_RXD,
187 O_TXD => O_TXD,
188 I_SWI => I_SWI,
189 I_BTN => I_BTN,
190 O_LED => O_LED,
191 O_ANO_N => O_ANO_N,
192 O_SEG_N => O_SEG_N,
193 O_MEM_CE_N => O_MEM_CE_N,
194 O_MEM_BE_N => O_MEM_BE_N,
195 O_MEM_WE_N => O_MEM_WE_N,
196 O_MEM_OE_N => O_MEM_OE_N,
197 O_MEM_ADV_N => O_MEM_ADV_N,
198 O_MEM_CLK => O_MEM_CLK,
199 O_MEM_CRE => O_MEM_CRE,
200 I_MEM_WAIT => I_MEM_WAIT,
201 O_MEM_ADDR => O_MEM_ADDR,
202 IO_MEM_DATA => IO_MEM_DATA,
203 O_PPCM_CE_N => O_PPCM_CE_N,
204 O_PPCM_RST_N => O_PPCM_RST_N,
205 O_FUSP_RTS_N => O_FUSP_RTS_N,
206 I_FUSP_CTS_N => I_FUSP_CTS_N,
207 I_FUSP_RXD => I_FUSP_RXD,
208 O_FUSP_TXD => O_FUSP_TXD,
209 I_FX2_IFCLK => I_FX2_IFCLK,
210 O_FX2_FIFO => O_FX2_FIFO,
211 I_FX2_FLAG => I_FX2_FLAG,
212 O_FX2_SLRD_N => O_FX2_SLRD_N,
213 O_FX2_SLWR_N => O_FX2_SLWR_N,
214 O_FX2_SLOE_N => O_FX2_SLOE_N,
215 O_FX2_PKTEND_N => O_FX2_PKTEND_N,
216 IO_FX2_DATA => IO_FX2_DATA
217 );
218
219 SERMSTR : entity work.serport_master_tb
220 generic map (
221 CDWIDTH => CLKDIV'length)
222 port map (
223 CLK => CLKCOM,
224 RESET => UART_RESET,
225 CLKDIV => CLKDIV,
227 ENAESC => '0',
229 RXVAL => UART_RXVAL,
230 RXERR => UART_RXERR,
231 RXOK => '1',
233 TXENA => UART_TXENA,
235 RXSD => UART_RXD,
236 TXSD => UART_TXD,
237 RXRTS_N => RTS_N,
238 TXCTS_N => CTS_N
239 );
240
241 FX2 : entity work.fx2_2fifo_core
242 port map (
243 CLK => CLKCOM,
244 RESET => '0',
246 RXENA => FX2_RXENA,
249 TXVAL => FX2_TXVAL,
251 FIFO => O_FX2_FIFO,
252 FLAG => I_FX2_FLAG,
258 );
259
260 proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
263 )
264 begin
265
266 if R_PORTSEL_FX2 = '0' then -- use serport
272 else -- otherwise use fx2
278 end if;
279
280 end process proc_fx2_mux;
281
282 proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
284 begin
285
286 if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
287 I_RXD <= UART_TXD; -- write port 0 inputs
288 UART_RXD <= O_TXD; -- get port 0 outputs
289 RTS_N <= '0';
290 I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
291 I_FUSP_CTS_N <= '0';
292 else -- otherwise use pmod1 rs232
293 I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
295 UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
297 I_RXD <= '1'; -- port 0 inputs to idle state
298 end if;
299
300 end process proc_ser_mux;
301
302 proc_moni: process
303 variable oline : line;
304 begin
305
306 loop
307 wait until rising_edge(CLKCOM);
308
309 if UART_RXERR = '1' then
310 writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
311 writeline(output, oline);
312 end if;
313
314 end loop;
315
316 end process proc_moni;
317
318 proc_simbus: process (SB_VAL)
319 begin
320 if SB_VAL'event and to_x01(SB_VAL)='1' then
321 if SB_ADDR = sbaddr_portsel then
322 R_PORTSEL_SER <= to_x01(SB_DATA(0));
323 R_PORTSEL_XON <= to_x01(SB_DATA(1));
324 R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
325 end if;
326 end if;
327 end process proc_simbus;
328
329end sim;
inout DATA slv8
in SLRD_N slbit
out RXBUSY slbit
out IFCLK slbit
out TXVAL slbit
out TXDATA slv8
in SLWR_N slbit
in SLOE_N slbit
in PKTEND_N slbit
VCO_DIVIDE positive := 1
GEN_TYPE string := "PLL"
CLKIN_PERIOD real := 10.0
OUT_DIVIDE positive := 1
in CLKIN slbit
CLKIN_JITTER real := 0.01
STARTUP_WAIT boolean := false
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in O_MEM_WE_N slbit
in O_MEM_ADV_N slbit
out I_MEM_WAIT slbit
in O_MEM_CLK slbit
in O_MEM_OE_N slbit
in O_MEM_ADDR slv23
in O_MEM_CRE slbit
in O_MEM_CE_N slbit
inout IO_MEM_DATA slv16
in O_MEM_BE_N slv2
slv2 :=( others => '0') O_FX2_FIFO
slv8 :=( others => 'Z') IO_FX2_DATA
slv8 :=( others => '0') UART_TXDATA
slv8 :=( others => '0') O_SEG_N
slv8 :=( others => '0') FX2_TXDATA
slv4 :=( others => '0') I_FX2_FLAG
Delay_length := 10 ns clock_period
slv8 :=( others => '0') FX2_RXDATA
slv2 :=( others => '1') O_MEM_BE_N
Delay_length := 200 ns clock_offset
slv16 :=( others => '0') IO_MEM_DATA
slv8 :=( others => '0') O_LED
slv23 :=( others => 'Z') O_MEM_ADDR
slv5 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv8 :=( others => '0') TBC_TXDATA
slv8 :=( others => '0') UART_RXDATA
slv8 :=( others => '0') I_SWI
slv4 :=( others => '0') O_ANO_N
slv8 :=( others => '0') TBC_RXDATA
Definition: xlib.vhd:35