39use ieee.std_logic_1164.
all;
40use ieee.numeric_std.
all;
41use ieee.std_logic_textio.
all;
155 UUT : nexys4_cram_aif
238 variable oline : line;
242 wait until rising_edge(CLKCOM);
246 writeline(output, oline);
251 end process proc_moni;
in CLKDIV slv( CDWIDTH- 1 downto 0)
VCO_MULTIPLY positive := 1
inout B slv( DWIDTH- 1 downto 0)
inout A slv( DWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
slbit := '1' TB_MEM_ADV_N
Delay_length := 10 ns clock_period
slv16 :=( others => '0') MM_MEM_DATA
slv16 :=( others => '0') O_LED
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slbit := '1' MM_MEM_ADV_N
slv2 :=( others => '1') TB_MEM_BE_N
slv16 :=( others => '0') TB_MEM_DATA
Delay_length := 1 ns pcb_delay
slv5 :=( others => '0') I_BTN
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED1
slv23 :=( others => 'Z') TB_MEM_ADDR
slv2 :=( others => '1') MM_MEM_BE_N
slv8 :=( others => '0') O_ANO_N
slv3 :=( others => '0') O_RGBLED0
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TXDATA
slv16 :=( others => '0') I_SWI
slv23 :=( others => 'Z') MM_MEM_ADDR