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W11 CPU core and support modules
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tb_nexys4_cram.vhd
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1-- $Id: tb_nexys4_cram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_nexys4_cram - sim
7-- Description: Test bench for nexys4 (base+cram)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_nexys4_core
14-- serport/tb/serport_master_tb
15-- nexys4_cram_aif [UUT]
16-- simlib/simbididly
17-- bplib/micron/mt45w8mw16b
18--
19-- To test: generic, any nexys4_cram_aif target
20--
21-- Target Devices: generic
22-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2018-11-03 1064 1.3.2 use sfs_gsim_core
27-- 2016-09-02 805 1.3.1 tbcore_rlink without CLK_STOP now
28-- 2016-07-20 791 1.3 use simbididly
29-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
30-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
31-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
32-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
33-- 2015-02-01 641 1.1 separate I_BTNRST_N
34-- 2013-09-28 535 1.0.1 use proper clock manager
35-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
36------------------------------------------------------------------------------
37
38library ieee;
39use ieee.std_logic_1164.all;
40use ieee.numeric_std.all;
41use ieee.std_logic_textio.all;
42use std.textio.all;
43
44use work.slvtypes.all;
45use work.rlinklib.all;
46use work.xlib.all;
47use work.nexys4lib.all;
48use work.simlib.all;
49use work.simbus.all;
50use work.sys_conf.all;
51
54
55architecture sim of tb_nexys4_cram is
56
57 signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
58 signal CLKCOM : slbit := '0'; -- communication clock
59
60 signal CLKCOM_CYCLE : integer := 0;
61
62 signal RESET : slbit := '0';
63 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
64 signal RXDATA : slv8 := (others=>'0');
65 signal RXVAL : slbit := '0';
66 signal RXERR : slbit := '0';
67 signal RXACT : slbit := '0';
68 signal TXDATA : slv8 := (others=>'0');
69 signal TXENA : slbit := '0';
70 signal TXBUSY : slbit := '0';
71
72 signal I_RXD : slbit := '1';
73 signal O_TXD : slbit := '1';
74 signal O_RTS_N : slbit := '0';
75 signal I_CTS_N : slbit := '0';
76 signal I_SWI : slv16 := (others=>'0');
77 signal I_BTN : slv5 := (others=>'0');
78 signal I_BTNRST_N : slbit := '1';
79 signal O_LED : slv16 := (others=>'0');
80 signal O_RGBLED0 : slv3 := (others=>'0');
81 signal O_RGBLED1 : slv3 := (others=>'0');
82 signal O_ANO_N : slv8 := (others=>'0');
83 signal O_SEG_N : slv8 := (others=>'0');
84
85 signal TB_MEM_CE_N : slbit := '1';
86 signal TB_MEM_BE_N : slv2 := (others=>'1');
87 signal TB_MEM_WE_N : slbit := '1';
88 signal TB_MEM_OE_N : slbit := '1';
89 signal TB_MEM_ADV_N : slbit := '1';
90 signal TB_MEM_CLK : slbit := '0';
91 signal TB_MEM_CRE : slbit := '0';
92 signal TB_MEM_WAIT : slbit := '0';
93 signal TB_MEM_ADDR : slv23 := (others=>'Z');
94 signal TB_MEM_DATA : slv16 := (others=>'0');
95
96 signal MM_MEM_CE_N : slbit := '1';
97 signal MM_MEM_BE_N : slv2 := (others=>'1');
98 signal MM_MEM_WE_N : slbit := '1';
99 signal MM_MEM_OE_N : slbit := '1';
100 signal MM_MEM_ADV_N : slbit := '1';
101 signal MM_MEM_CLK : slbit := '0';
102 signal MM_MEM_CRE : slbit := '0';
103 signal MM_MEM_WAIT : slbit := '0';
104 signal MM_MEM_ADDR : slv23 := (others=>'Z');
105 signal MM_MEM_DATA : slv16 := (others=>'0');
106
107 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
108
109 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
110
111 constant clock_period : Delay_length := 10 ns;
112 constant clock_offset : Delay_length := 200 ns;
113 constant pcb_delay : Delay_length := 1 ns;
114
115begin
116
117 CLKGEN : simclk
118 generic map (
121 port map (
122 CLK => CLKOSC
123 );
124
125 CLKGEN_COM : sfs_gsim_core
126 generic map (
127 VCO_DIVIDE => sys_conf_clkser_vcodivide,
128 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
129 OUT_DIVIDE => sys_conf_clkser_outdivide)
130 port map (
131 CLKIN => CLKOSC,
132 CLKFX => CLKCOM,
133 LOCKED => open
134 );
135
136 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
137
138 TBCORE : entity work.tbcore_rlink
139 port map (
140 CLK => CLKCOM,
141 RX_DATA => TXDATA,
142 RX_VAL => TXENA,
143 RX_HOLD => TXBUSY,
144 TX_DATA => RXDATA,
145 TX_ENA => RXVAL
146 );
147
148 N4CORE : entity work.tb_nexys4_core
149 port map (
150 I_SWI => I_SWI,
151 I_BTN => I_BTN,
153 );
154
155 UUT : nexys4_cram_aif
156 port map (
157 I_CLK100 => CLKOSC,
158 I_RXD => I_RXD,
159 O_TXD => O_TXD,
160 O_RTS_N => O_RTS_N,
161 I_CTS_N => I_CTS_N,
162 I_SWI => I_SWI,
163 I_BTN => I_BTN,
164 I_BTNRST_N => I_BTNRST_N,
165 O_LED => O_LED,
166 O_RGBLED0 => O_RGBLED0,
167 O_RGBLED1 => O_RGBLED1,
168 O_ANO_N => O_ANO_N,
169 O_SEG_N => O_SEG_N,
170 O_MEM_CE_N => TB_MEM_CE_N,
171 O_MEM_BE_N => TB_MEM_BE_N,
172 O_MEM_WE_N => TB_MEM_WE_N,
173 O_MEM_OE_N => TB_MEM_OE_N,
174 O_MEM_ADV_N => TB_MEM_ADV_N,
175 O_MEM_CLK => TB_MEM_CLK,
176 O_MEM_CRE => TB_MEM_CRE,
177 I_MEM_WAIT => TB_MEM_WAIT,
178 O_MEM_ADDR => TB_MEM_ADDR,
179 IO_MEM_DATA => TB_MEM_DATA
180 );
181
191
192 BUSDLY: simbididly
193 generic map (
194 DELAY => pcb_delay,
195 DWIDTH => 16)
196 port map (
197 A => TB_MEM_DATA,
199
200 MEM : entity work.mt45w8mw16b
201 port map (
202 CLK => MM_MEM_CLK,
203 CE_N => MM_MEM_CE_N,
204 OE_N => MM_MEM_OE_N,
205 WE_N => MM_MEM_WE_N,
206 UB_N => MM_MEM_BE_N(1),
207 LB_N => MM_MEM_BE_N(0),
209 CRE => MM_MEM_CRE,
211 ADDR => MM_MEM_ADDR,
213 );
214
215 SERMSTR : entity work.serport_master_tb
216 generic map (
217 CDWIDTH => CLKDIV'length)
218 port map (
219 CLK => CLKCOM,
220 RESET => RESET,
221 CLKDIV => CLKDIV,
223 ENAESC => '0',
224 RXDATA => RXDATA,
225 RXVAL => RXVAL,
226 RXERR => RXERR,
227 RXOK => '1',
228 TXDATA => TXDATA,
229 TXENA => TXENA,
230 TXBUSY => TXBUSY,
231 RXSD => O_TXD,
232 TXSD => I_RXD,
233 RXRTS_N => I_CTS_N,
235 );
236
237 proc_moni: process
238 variable oline : line;
239 begin
240
241 loop
242 wait until rising_edge(CLKCOM);
243
244 if RXERR = '1' then
245 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
246 writeline(output, oline);
247 end if;
248
249 end loop;
250
251 end process proc_moni;
252
253end sim;
in UB_N slbit
Definition: mt45w8mw16b.vhd:64
in CRE slbit
Definition: mt45w8mw16b.vhd:67
in WE_N slbit
Definition: mt45w8mw16b.vhd:63
in CLK slbit
Definition: mt45w8mw16b.vhd:60
out MWAIT slbit
Definition: mt45w8mw16b.vhd:68
in CE_N slbit
Definition: mt45w8mw16b.vhd:61
in OE_N slbit
Definition: mt45w8mw16b.vhd:62
in ADV_N slbit
Definition: mt45w8mw16b.vhd:66
in LB_N slbit
Definition: mt45w8mw16b.vhd:65
inout DATA slv16
Definition: mt45w8mw16b.vhd:71
in ADDR slv23
Definition: mt45w8mw16b.vhd:69
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
inout B slv( DWIDTH- 1 downto 0)
Definition: simbididly.vhd:32
inout A slv( DWIDTH- 1 downto 0)
Definition: simbididly.vhd:30
DELAY Delay_length
Definition: simbididly.vhd:27
DWIDTH positive := 16
Definition: simbididly.vhd:28
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
out I_BTNRST_N slbit
out I_SWI slv16
slbit := '0' RXERR
slbit := '0' RESET
slv8 :=( others => '0') O_SEG_N
integer := 0 CLKCOM_CYCLE
slbit := '1' I_BTNRST_N
slbit := '1' TB_MEM_ADV_N
Delay_length := 10 ns clock_period
slv2 := "00" CLKDIV
slv16 :=( others => '0') MM_MEM_DATA
slv16 :=( others => '0') O_LED
slbit := '0' TB_MEM_CRE
slbit := '0' TXENA
slv8 :=( others => '0') RXDATA
Delay_length := 200 ns clock_offset
slbit := '1' MM_MEM_OE_N
slbit := '0' TB_MEM_CLK
slbit := '0' MM_MEM_CRE
slbit := '1' MM_MEM_ADV_N
slbit := '1' MM_MEM_CE_N
slv2 :=( others => '1') TB_MEM_BE_N
slbit := '1' TB_MEM_WE_N
slbit := '0' RXACT
slv16 :=( others => '0') TB_MEM_DATA
slbit := '1' MM_MEM_WE_N
Delay_length := 1 ns pcb_delay
slv5 :=( others => '0') I_BTN
slbit := '0' RXVAL
slbit := '1' O_TXD
slbit := '0' I_CTS_N
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED1
slbit := '0' CLKOSC
slbit := '1' TB_MEM_OE_N
slbit := '0' O_RTS_N
slv23 :=( others => 'Z') TB_MEM_ADDR
slv2 :=( others => '1') MM_MEM_BE_N
slbit := '0' CLKCOM
slbit := '0' MM_MEM_WAIT
slv8 :=( others => '0') O_ANO_N
slbit := '0' TXBUSY
slv3 :=( others => '0') O_RGBLED0
slbit := '0' MM_MEM_CLK
slbit := '0' R_PORTSEL_XON
slbit := '0' TB_MEM_WAIT
slv8 :=( others => '0') TXDATA
slv16 :=( others => '0') I_SWI
slbit := '1' TB_MEM_CE_N
slv23 :=( others => 'Z') MM_MEM_ADDR
slbit := '1' I_RXD
Definition: xlib.vhd:35