w11 - vhd 0.794
W11 CPU core and support modules
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tb_sramif2migui_core.vhd
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1-- $Id: tb_sramif2migui_core.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_sramif2migui_core - sim
7-- Description: Test bench for sramif2migui_core and migui_core_gsim
8--
9-- Dependencies: vlib/simlib/simclk
10-- vlib/simlib/simclkcnt
11-- migui_core_gsim
12-- sramif2migui_core
13-- migui_core_gsim
14-- migui2bram
15--
16-- To test: sramif2migui_core
17--
18-- Target Devices: generic
19-- Tool versions: viv 2017.2; ghdl 0.34
20-- Revision History:
21-- Date Rev Version Comment
22-- 2018-12-25 1093 1.0 Initial version
23-- 2018-11-10 1067 0.1 First draft (derived fr tb_nx_cram_memctl.vhd)
24------------------------------------------------------------------------------
25
26library ieee;
27use ieee.std_logic_1164.all;
28use ieee.numeric_std.all;
29use ieee.std_logic_textio.all;
30use std.textio.all;
31
32use work.slvtypes.all;
33use work.simlib.all;
34use work.miglib.all;
35use work.sys_conf.all;
36
39
40architecture sim of tb_sramif2migui_core is
41
42 constant clkmui_mul : positive := 6;
43 constant clkmui_div : positive := 12;
44
45 constant c_caco_wait : positive := 50; -- UI_CLK cycles till CALIB_COMP = 1
46
47 constant mwidth : positive := 2**sys_conf_bawidth; -- mask width (8 or 16)
48 constant dwidth : positive := 8*mwidth; -- data width (64 or 128)
49
50 signal CLK : slbit := '0';
51 signal RESET : slbit := '0';
52 signal REQ : slbit := '0';
53 signal WE : slbit := '0';
54 signal BUSY : slbit := '0';
55 signal ACK_R : slbit := '0';
56 signal ACK_W : slbit := '0';
57 signal ACT_R : slbit := '0';
58 signal ACT_W : slbit := '0';
59 signal ADDR : slv20 := (others=>'0');
60 signal BE : slv4 := (others=>'0');
61 signal DI : slv32 := (others=>'0');
62 signal DO : slv32 := (others=>'0');
63 signal MONI : sramif2migui_moni_type := sramif2migui_moni_init;
64
65 signal SYS_CLK : slbit := '0';
66 signal SYS_RST : slbit := '0';
67
68 signal UI_CLK : slbit := '0';
69 signal UI_CLK_SYNC_RST : slbit := '0';
70 signal INIT_CALIB_COMPLETE : slbit := '0';
71 signal APP_RDY : slbit := '0';
72 signal APP_EN : slbit := '0';
73 signal APP_CMD : slv3:= (others=>'0');
74 signal APP_ADDR : slv(sys_conf_mawidth-1 downto 0):= (others=>'0');
75 signal APP_WDF_RDY : slbit := '0';
76 signal APP_WDF_WREN : slbit := '0';
77 signal APP_WDF_DATA : slv(dwidth-1 downto 0):= (others=>'0');
78 signal APP_WDF_MASK : slv(mwidth-1 downto 0):= (others=>'0');
79 signal APP_WDF_END : slbit := '0';
80 signal APP_RD_DATA_VALID : slbit := '0';
81 signal APP_RD_DATA : slv(dwidth-1 downto 0):= (others=>'0');
82 signal APP_RD_DATA_END : slbit := '0';
83
84 signal R_MEMON : slbit := '0';
85 signal N_CHK_DATA : slbit := '0';
86 signal N_REF_DATA : slv32 := (others=>'0');
87 signal N_REF_ADDR : slv20 := (others=>'0');
88 signal R_CHK_DATA_AL : slbit := '0';
89 signal R_REF_DATA_AL : slv32 := (others=>'0');
90 signal R_REF_ADDR_AL : slv20 := (others=>'0');
91 signal R_CHK_DATA_DL : slbit := '0';
92 signal R_REF_DATA_DL : slv32 := (others=>'0');
93 signal R_REF_ADDR_DL : slv20 := (others=>'0');
94
95 signal R_NRDRHIT : integer := 0;
96 signal R_NWRRHIT : integer := 0;
97 signal R_NWRFLUSH : integer := 0;
98 signal R_NMIGCBUSY : integer := 0;
99 signal R_NMIGWBUSY : integer := 0;
100 signal R_NMIGCACOW : integer := 0;
101
102 signal CLK_STOP : slbit := '0';
103 signal CLK_CYCLE : integer := 0;
104 signal UI_CLK_CYCLE : integer := 0;
105
106 constant clock_period : Delay_length := 12.5 ns;
107 constant clock_offset : Delay_length := 200 ns;
108 constant setup_time : Delay_length := 3 ns;
109 constant c2out_time : Delay_length := 5 ns;
110
111 constant sysclock_period : Delay_length := 5.833 ns;
112 constant sysclock_offset : Delay_length := 200 ns;
113
114begin
115
116 USRCLKGEN : simclk
117 generic map (
120 port map (
121 CLK => CLK,
123 );
124
125 SYSCLKGEN : simclk
126 generic map (
129 port map (
130 CLK => SYS_CLK,
132 );
133
134 CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
135 UICLKCNT : simclkcnt port map (CLK => UI_CLK, CLK_CYCLE => UI_CLK_CYCLE);
136
137 SR2MU : sramif2migui_core
138 generic map (
139 BAWIDTH => sys_conf_bawidth,
140 MAWIDTH => sys_conf_mawidth)
141 port map (
142 CLK => CLK,
143 RESET => RESET,
144 REQ => REQ,
145 WE => WE,
146 BUSY => BUSY,
147 ACK_R => ACK_R,
148 ACK_W => ACK_W,
149 ACT_R => ACT_R,
150 ACT_W => ACT_W,
151 ADDR => ADDR,
152 BE => BE,
153 DI => DI,
154 DO => DO,
155 MONI => MONI,
156 UI_CLK => UI_CLK,
159 APP_RDY => APP_RDY,
160 APP_EN => APP_EN,
161 APP_CMD => APP_CMD,
171 );
172
173 BTYP_MSIM : if sys_conf_btyp = c_btyp_msim generate
174 I0 : migui_core_gsim
175 generic map (
176 BAWIDTH => sys_conf_bawidth,
177 MAWIDTH => sys_conf_mawidth,
178 SAWIDTH => sys_conf_sawidth,
181 port map (
182 SYS_CLK => SYS_CLK,
183 SYS_RST => SYS_RST,
184 UI_CLK => UI_CLK,
187 APP_RDY => APP_RDY,
188 APP_EN => APP_EN,
189 APP_CMD => APP_CMD,
199 APP_REF_REQ => '0',
200 APP_ZQ_REQ => '0',
201 APP_REF_ACK => open,
202 APP_ZQ_ACK => open
203 );
204 end generate BTYP_MSIM;
205
206 BTYP_BRAM : if sys_conf_btyp = c_btyp_bram generate
207 I0 : migui2bram
208 generic map (
209 BAWIDTH => sys_conf_bawidth,
210 MAWIDTH => sys_conf_mawidth,
211 RAWIDTH => sys_conf_rawidth,
212 RDELAY => sys_conf_rdelay,
215 CLKMSYS_PERIOD => 6.000)
216 port map (
217 SYS_CLK => SYS_CLK,
218 SYS_RST => SYS_RST,
219 UI_CLK => UI_CLK,
222 APP_RDY => APP_RDY,
223 APP_EN => APP_EN,
224 APP_CMD => APP_CMD,
234 );
235 end generate BTYP_BRAM;
236
237 proc_stim: process
238 file fstim : text open read_mode is "tb_sramif2migui_core_stim";
239 variable iline : line;
240 variable oline : line;
241 variable ok : boolean;
242 variable dname : string(1 to 6) := (others=>' ');
243 variable idelta : integer := 0;
244 variable iaddr : slv20 := (others=>'0');
245 variable idata : slv32 := (others=>'0');
246 variable ibe : slv4 := (others=>'0');
247 variable ival : slbit := '0';
248 variable nbusy : integer := 0;
249 variable nwreq : natural := 0;
250 variable nrdrhit : integer := 0;
251 variable nwrrhit : integer := 0;
252 variable nwrflush : integer := 0;
253 variable nmigcbusy : integer := 0;
254 variable nmigwbusy : integer := 0;
255 variable nmigcacow : integer := 0;
256
257 begin
258
259 wait for clock_offset - setup_time;
260
261 file_loop: while not endfile(fstim) loop
262
263 readline (fstim, iline);
264
265 readcomment(iline, ok);
266 next file_loop when ok;
267
268 readword(iline, dname, ok);
269 if ok then
270 case dname is
271 when ".memon" => -- .memon
272 read_ea(iline, ival);
273 R_MEMON <= ival;
274 wait for 2*clock_period;
275
276 when ".reset" => -- .reset
277 write(oline, string'(".reset"));
278 writeline(output, oline);
279 RESET <= '1';
280 wait for clock_period;
281 RESET <= '0';
282 wait for 9*clock_period;
283
284 when ".wreq " => -- .wreq
285 read_ea(iline, nwreq);
286
287 when ".wait " => -- .wait
288 read_ea(iline, idelta);
289 wait for idelta*clock_period;
290
291 when "read " => -- read
292 readgen_ea(iline, iaddr, 16);
293 readgen_ea(iline, idata, 16);
294 ADDR <= iaddr;
295 REQ <= '1';
296 WE <= '0';
297
298 writetimestamp(oline, CLK_CYCLE, ": stim read ");
299 writegen(oline, iaddr, right, 6, 16);
300 write(oline, string'(" "));
301 writegen(oline, idata, right, 9, 16);
302
303 nbusy := 0;
304 while BUSY = '1' loop
305 nbusy := nbusy + 1;
306 wait for clock_period;
307 end loop;
308
309 write(oline, string'(" nb="));
310 write(oline, nbusy, right, 2);
311 write(oline, string'(" mo="));
312 write(oline, R_NRDRHIT-nrdrhit, right, 2);
313 write(oline, R_NWRRHIT-nwrrhit, right, 2);
314 write(oline, R_NWRFLUSH-nwrflush, right, 2);
315 write(oline, R_NMIGCBUSY-nmigcbusy, right, 2);
316 write(oline, R_NMIGWBUSY-nmigwbusy, right, 2);
317 write(oline, string'(" "));
318 write(oline, R_NMIGCACOW-nmigcacow, right, 1);
319 writeline(output, oline);
320 nrdrhit := R_NRDRHIT;
321 nwrrhit := R_NWRRHIT;
322 nwrflush := R_NWRFLUSH;
323 nmigcbusy := R_NMIGCBUSY;
324 nmigwbusy := R_NMIGWBUSY;
325 nmigcacow := R_NMIGCACOW;
326
327 N_CHK_DATA <= '1', '0' after clock_period;
328 N_REF_DATA <= idata;
329 N_REF_ADDR <= iaddr;
330
331 wait for clock_period;
332 REQ <= '0';
333 if nwreq > 0 then wait for nwreq*clock_period; end if;
334
335 when "write " => -- write
336 readgen_ea(iline, iaddr, 16);
337 read_ea(iline, ibe);
338 readgen_ea(iline, idata, 16);
339 ADDR <= iaddr;
340 BE <= ibe;
341 DI <= idata;
342 REQ <= '1';
343 WE <= '1';
344
345 writetimestamp(oline, CLK_CYCLE, ": stim write");
346 writegen(oline, iaddr, right, 6, 16);
347 writegen(oline, ibe , right, 5, 2);
348 writegen(oline, idata, right, 9, 16);
349
350 nbusy := 0;
351 while BUSY = '1' loop
352 nbusy := nbusy + 1;
353 wait for clock_period;
354 end loop;
355
356 write(oline, string'(" nb="));
357 write(oline, nbusy, right, 2);
358 write(oline, string'(" mo="));
359 write(oline, R_NRDRHIT-nrdrhit, right, 2);
360 write(oline, R_NWRRHIT-nwrrhit, right, 2);
361 write(oline, R_NWRFLUSH-nwrflush, right, 2);
362 write(oline, R_NMIGCBUSY-nmigcbusy, right, 2);
363 write(oline, R_NMIGWBUSY-nmigwbusy, right, 2);
364 write(oline, string'(" "));
365 write(oline, R_NMIGCACOW-nmigcacow, right, 1);
366 writeline(output, oline);
367 nrdrhit := R_NRDRHIT;
368 nwrrhit := R_NWRRHIT;
369 nwrflush := R_NWRFLUSH;
370 nmigcbusy := R_NMIGCBUSY;
371 nmigwbusy := R_NMIGWBUSY;
372 nmigcacow := R_NMIGCACOW;
373
374 wait for clock_period;
375 REQ <= '0';
376 if nwreq > 0 then wait for nwreq*clock_period; end if;
377
378 when others => -- bad directive
379 write(oline, string'("?? unknown directive: "));
380 write(oline, dname);
381 writeline(output, oline);
382 report "aborting" severity failure;
383 end case;
384 else
385 report "failed to find command" severity failure;
386
387 end if;
388
389 testempty_ea(iline);
390
391 end loop; -- file fstim
392
393 wait for 10*clock_period;
394
395 writetimestamp(oline, CLK_CYCLE, ": stat moni-cnt= ");
396 write(oline, R_NRDRHIT, right, 5);
397 write(oline, string'(","));
398 write(oline, R_NWRRHIT, right, 5);
399 write(oline, string'(","));
400 write(oline, R_NWRFLUSH, right, 5);
401 write(oline, string'(","));
402 write(oline, R_NMIGCBUSY, right, 5);
403 write(oline, string'(","));
404 write(oline, R_NMIGWBUSY, right, 5);
405 write(oline, string'(","));
406 write(oline, R_NMIGCACOW, right, 5);
407 writeline(output, oline);
408
409 writetimestamp(oline, CLK_CYCLE, ": DONE ");
410 writeline(output, oline);
411
412 CLK_STOP <= '1';
413
414 wait; -- suspend proc_stim forever
415 -- clock is stopped, sim will end
416
417 end process proc_stim;
418
419
420 proc_moni: process
421 variable oline : line;
422 begin
423
424 loop
425 wait until rising_edge(CLK);
426
427 -- performance counter
428 if MONI.rdrhit = '1' then
429 R_NRDRHIT <= R_NRDRHIT + 1;
430 end if;
431 if MONI.wrrhit = '1' then
432 R_NWRRHIT <= R_NWRRHIT + 1;
433 end if;
434 if MONI.wrflush = '1' then
435 R_NWRFLUSH <= R_NWRFLUSH + 1;
436 end if;
437 if MONI.migcbusy = '1' then
439 end if;
440 if MONI.migwbusy = '1' then
442 end if;
443 if MONI.migcacow = '1' then
445 end if;
446
447 if ACK_R = '1' then
448 writetimestamp(oline, CLK_CYCLE, ": moni ");
449 writegen(oline, DO, right, 9, 16);
450 if R_CHK_DATA_DL = '1' then
451 write(oline, string'(" CHECK"));
452 if R_REF_DATA_DL = DO then
453 write(oline, string'(" OK"));
454 else
455 write(oline, string'(" FAIL, exp="));
456 writegen(oline, R_REF_DATA_DL, right, 9, 16);
457 write(oline, string'(" for a="));
458 writegen(oline, R_REF_ADDR_DL, right, 5, 16);
459 end if;
460 R_CHK_DATA_DL <= '0';
461 end if;
462 writeline(output, oline);
463 end if;
464
465 if R_CHK_DATA_AL = '1' then
469 R_CHK_DATA_AL <= '0';
470 end if;
471 if N_CHK_DATA = '1' then
475 end if;
476
477 end loop;
478
479 end process proc_moni;
480
481
482 proc_memon: process
483 variable oline : line;
484 begin
485
486 loop
487 wait until rising_edge(UI_CLK);
488
489 if R_MEMON = '1' then
490 if APP_EN = '1' then
491 writetimestamp(oline, UI_CLK_CYCLE, ": mreq ");
492 write(oline, APP_CMD, right, 3);
493 write(oline, string'(","));
494 write(oline, APP_RDY, right);
495 write(oline, string'(","));
496 write(oline, APP_WDF_RDY, right);
497 writegen(oline,
498 APP_ADDR(sys_conf_sawidth-sys_conf_bawidth-1 downto 0),
499 right, 7, 16);
500 write(oline, APP_WDF_WREN, right, 2);
501 write(oline, APP_WDF_END, right, 2);
502 if APP_WDF_WREN = '1' then
503 writegen(oline, APP_WDF_MASK, right, (mwidth/4)+1, 16);
504 writegen(oline, APP_WDF_DATA, right, (dwidth/4)+1, 16);
505 end if;
506 writeline(output, oline);
507 end if;
508
509 if APP_RD_DATA_VALID = '1' then
510 writetimestamp(oline, UI_CLK_CYCLE, ": mres ");
511 write(oline, APP_RD_DATA_END, right);
512 writegen(oline, APP_RD_DATA, right, (dwidth/4)+1, 16);
513 writeline(output, oline);
514 end if;
515
516 end if;
517
518 end loop;
519
520 end process proc_memon;
521
522
523end sim;
MAWIDTH positive := 28
Definition: migui2bram.vhd:35
out UI_CLK slbit
Definition: migui2bram.vhd:44
out APP_RDY slbit
Definition: migui2bram.vhd:47
out APP_RD_DATA_VALID slbit
Definition: migui2bram.vhd:56
out APP_RD_DATA_END slbit
Definition: migui2bram.vhd:59
in APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
Definition: migui2bram.vhd:54
in SYS_CLK slbit
Definition: migui2bram.vhd:42
CLKMSYS_PERIOD real := 6.000
Definition: migui2bram.vhd:40
CLKMUI_MUL positive := 6
Definition: migui2bram.vhd:38
in APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
Definition: migui2bram.vhd:53
in APP_WDF_END slbit
Definition: migui2bram.vhd:55
RDELAY positive := 5
Definition: migui2bram.vhd:37
out INIT_CALIB_COMPLETE slbit
Definition: migui2bram.vhd:46
out APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
Definition: migui2bram.vhd:57
in SYS_RST slbit
Definition: migui2bram.vhd:43
RAWIDTH positive := 19
Definition: migui2bram.vhd:36
out APP_WDF_RDY slbit
Definition: migui2bram.vhd:51
CLKMUI_DIV positive := 12
Definition: migui2bram.vhd:39
in APP_WDF_WREN slbit
Definition: migui2bram.vhd:52
in APP_EN slbit
Definition: migui2bram.vhd:48
in APP_ADDR slv( MAWIDTH- 1 downto 0)
Definition: migui2bram.vhd:50
in APP_CMD slv3
Definition: migui2bram.vhd:49
BAWIDTH positive := 4
Definition: migui2bram.vhd:34
out UI_CLK_SYNC_RST slbit
Definition: migui2bram.vhd:45
MAWIDTH positive := 28
out APP_RDY slbit
out APP_RD_DATA_VALID slbit
out APP_REF_ACK slbit
out APP_RD_DATA_END slbit
in APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
CLKMUI_MUL positive := 6
SAWIDTH positive := 24
in APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
in APP_WDF_END slbit
out INIT_CALIB_COMPLETE slbit
out APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
in APP_REF_REQ slbit
out APP_ZQ_ACK slbit
out APP_WDF_RDY slbit
in APP_ZQ_REQ slbit
CLKMUI_DIV positive := 12
in APP_WDF_WREN slbit
in APP_ADDR slv( MAWIDTH- 1 downto 0)
BAWIDTH positive := 4
out UI_CLK_SYNC_RST slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
in CLK_STOP slbit := '0'
Definition: simclk.vhd:35
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 19 downto 0) slv20
Definition: slvtypes.vhd:53
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector slv
Definition: slvtypes.vhd:31
MAWIDTH positive := 28
in INIT_CALIB_COMPLETE slbit
out MONI sramif2migui_moni_type
in APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out APP_ADDR slv( MAWIDTH- 1 downto 0)
out APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
BAWIDTH positive := 4
slv32 :=( others => '0') R_REF_DATA_DL
slv( mwidth- 1 downto 0) :=( others => '0') APP_WDF_MASK
slv4 :=( others => '0') BE
slv32 :=( others => '0') DO
Delay_length := 3 ns setup_time
slv20 :=( others => '0') R_REF_ADDR_AL
slv20 :=( others => '0') N_REF_ADDR
positive := 8* mwidth dwidth
Delay_length := 200 ns clock_offset
slv20 :=( others => '0') ADDR
slv3 :=( others => '0') APP_CMD
slv20 :=( others => '0') R_REF_ADDR_DL
positive := 2** sys_conf_bawidth mwidth
Delay_length := 5.833 ns sysclock_period
sramif2migui_moni_type := sramif2migui_moni_init MONI
slv32 :=( others => '0') DI
slv( sys_conf_mawidth- 1 downto 0) :=( others => '0') APP_ADDR
slv( dwidth- 1 downto 0) :=( others => '0') APP_WDF_DATA
slv32 :=( others => '0') N_REF_DATA
Delay_length := 200 ns sysclock_offset
Delay_length := 12.5 ns clock_period
slv32 :=( others => '0') R_REF_DATA_AL
Delay_length := 5 ns c2out_time
slv( dwidth- 1 downto 0) :=( others => '0') APP_RD_DATA