27use ieee.std_logic_1164.
all;
28use ieee.numeric_std.
all;
29use ieee.std_logic_textio.
all;
47 constant mwidth : positive := 2**sys_conf_bawidth;
63 signal MONI : sramif2migui_moni_type := sramif2migui_moni_init;
74 signal APP_ADDR : slv(sys_conf_mawidth-1 downto 0):= (others=>'0');
173 BTYP_MSIM : if sys_conf_btyp = c_btyp_msim generate
204 end generate BTYP_MSIM;
206 BTYP_BRAM : if sys_conf_btyp = c_btyp_bram generate
212 RDELAY => sys_conf_rdelay,
235 end generate BTYP_BRAM;
238 file fstim : text open read_mode is "tb_sramif2migui_core_stim";
239 variable iline : line;
240 variable oline : line;
241 variable ok : boolean;
242 variable dname : string(1 to 6) := (others=>' ');
243 variable idelta : integer := 0;
244 variable iaddr : slv20 := (others=>'0');
245 variable idata : slv32 := (others=>'0');
246 variable ibe : slv4 := (others=>'0');
247 variable ival : slbit := '0';
248 variable nbusy : integer := 0;
249 variable nwreq : natural := 0;
250 variable nrdrhit : integer := 0;
251 variable nwrrhit : integer := 0;
252 variable nwrflush : integer := 0;
253 variable nmigcbusy : integer := 0;
254 variable nmigwbusy : integer := 0;
255 variable nmigcacow : integer := 0;
261 file_loop: while not endfile(fstim) loop
263 readline (fstim, iline);
265 readcomment(iline, ok);
266 next file_loop when ok;
268 readword(iline, dname, ok);
272 read_ea(iline, ival);
277 write(oline, string'(".reset"));
278 writeline(output, oline);
285 read_ea(iline, nwreq);
288 read_ea(iline, idelta);
292 readgen_ea(iline, iaddr, 16);
293 readgen_ea(iline, idata, 16);
298 writetimestamp(oline, CLK_CYCLE, ": stim read ");
299 writegen(oline, iaddr, right, 6, 16);
300 write(oline, string'(" "));
301 writegen(oline, idata, right, 9, 16);
304 while BUSY = '1' loop
309 write(oline, string'(" nb="));
310 write(oline, nbusy, right, 2);
311 write(oline, string'(" mo="));
312 write(oline, R_NRDRHIT-nrdrhit, right, 2);
313 write(oline, R_NWRRHIT-nwrrhit, right, 2);
317 write(oline, string'(" "));
319 writeline(output, oline);
336 readgen_ea(iline, iaddr, 16);
338 readgen_ea(iline, idata, 16);
345 writetimestamp(oline, CLK_CYCLE, ": stim write");
346 writegen(oline, iaddr, right, 6, 16);
347 writegen(oline, ibe , right, 5, 2);
348 writegen(oline, idata, right, 9, 16);
351 while BUSY = '1' loop
356 write(oline, string'(" nb="));
357 write(oline, nbusy, right, 2);
358 write(oline, string'(" mo="));
359 write(oline, R_NRDRHIT-nrdrhit, right, 2);
360 write(oline, R_NWRRHIT-nwrrhit, right, 2);
364 write(oline, string'(" "));
366 writeline(output, oline);
379 write(oline, string'("?? unknown directive: "));
381 writeline(output, oline);
382 report "aborting" severity failure;
385 report "failed to find command" severity failure;
395 writetimestamp(oline, CLK_CYCLE, ": stat moni-cnt= ");
397 write(oline, string'(","));
399 write(oline, string'(","));
401 write(oline, string'(","));
403 write(oline, string'(","));
405 write(oline, string'(","));
407 writeline(output, oline);
409 writetimestamp(oline, CLK_CYCLE, ": DONE ");
410 writeline(output, oline);
417 end process proc_stim;
421 variable oline : line;
425 wait until rising_edge(CLK);
428 if MONI.rdrhit = '1' then
431 if MONI.wrrhit = '1' then
434 if MONI.wrflush = '1' then
437 if MONI.migcbusy = '1' then
440 if MONI.migwbusy = '1' then
443 if MONI.migcacow = '1' then
448 writetimestamp(oline, CLK_CYCLE, ": moni ");
449 writegen(oline, DO, right, 9, 16);
451 write(oline, string'(" CHECK"));
453 write(oline, string'(" OK"));
455 write(oline, string'(" FAIL, exp="));
457 write(oline, string'(" for a="));
462 writeline(output, oline);
479 end process proc_moni;
483 variable oline : line;
487 wait until rising_edge(UI_CLK);
492 write(oline, APP_CMD, right, 3);
493 write(oline, string'(","));
495 write(oline, string'(","));
498 APP_ADDR(sys_conf_sawidth-sys_conf_bawidth-1 downto 0),
506 writeline(output, oline);
513 writeline(output, oline);
520 end process proc_memon;
out APP_RD_DATA_VALID slbit
out APP_RD_DATA_END slbit
in APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
CLKMSYS_PERIOD real := 6.000
in APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out INIT_CALIB_COMPLETE slbit
out APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
CLKMUI_DIV positive := 12
in APP_ADDR slv( MAWIDTH- 1 downto 0)
out UI_CLK_SYNC_RST slbit
out APP_RD_DATA_VALID slbit
out APP_RD_DATA_END slbit
in APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
in APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out INIT_CALIB_COMPLETE slbit
out APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
CLKMUI_DIV positive := 12
in APP_ADDR slv( MAWIDTH- 1 downto 0)
out UI_CLK_SYNC_RST slbit
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 19 downto 0) slv20
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 31 downto 0) slv32
in APP_RD_DATA_VALID slbit
in INIT_CALIB_COMPLETE slbit
out MONI sramif2migui_moni_type
in APP_RD_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out APP_WDF_DATA slv( 8*( 2** BAWIDTH)- 1 downto 0)
out APP_ADDR slv( MAWIDTH- 1 downto 0)
out APP_WDF_MASK slv(( 2** BAWIDTH)- 1 downto 0)
slv32 :=( others => '0') R_REF_DATA_DL
slv( mwidth- 1 downto 0) :=( others => '0') APP_WDF_MASK
slv4 :=( others => '0') BE
slv32 :=( others => '0') DO
Delay_length := 3 ns setup_time
slbit := '0' R_CHK_DATA_DL
slv20 :=( others => '0') R_REF_ADDR_AL
slv20 :=( others => '0') N_REF_ADDR
positive := 8* mwidth dwidth
slbit := '0' APP_RD_DATA_VALID
slbit := '0' APP_RD_DATA_END
positive := 50 c_caco_wait
Delay_length := 200 ns clock_offset
positive := 12 clkmui_div
slv20 :=( others => '0') ADDR
slbit := '0' UI_CLK_SYNC_RST
slv3 :=( others => '0') APP_CMD
slbit := '0' R_CHK_DATA_AL
slv20 :=( others => '0') R_REF_ADDR_DL
positive := 2** sys_conf_bawidth mwidth
Delay_length := 5.833 ns sysclock_period
sramif2migui_moni_type := sramif2migui_moni_init MONI
slv32 :=( others => '0') DI
slv( sys_conf_mawidth- 1 downto 0) :=( others => '0') APP_ADDR
slv( dwidth- 1 downto 0) :=( others => '0') APP_WDF_DATA
slv32 :=( others => '0') N_REF_DATA
slbit := '0' APP_WDF_WREN
Delay_length := 200 ns sysclock_offset
slbit := '0' INIT_CALIB_COMPLETE
Delay_length := 12.5 ns clock_period
integer := 0 UI_CLK_CYCLE
slv32 :=( others => '0') R_REF_DATA_AL
Delay_length := 5 ns c2out_time
slv( dwidth- 1 downto 0) :=( others => '0') APP_RD_DATA