30use ieee.std_logic_1164.
all;
31use ieee.numeric_std.
all;
57 MONI : out serport_moni_type;
122 report "assert(CDWIDTH<=16): max width of UART clock divider"
128 POUT_SINGLE => false,
242 constant rxsize_rxok_off
: slv2 := "01";
243 constant rxsize_rxok_on
: slv2 := "10";
244 variable rxsize_msb : slv2 := "00";
246 if rising_edge(CLKS) then
251 if unsigned(rxsize_msb) < unsigned(rxsize_rxok_off) then
253 elsif unsigned(RXSIZE_MSB) >= unsigned(rxsize_rxok_on) then
258 end process proc_rxok;
272 end process proc_cts;
354 MONI.abclkdiv <= (others=>'0');
357 end process proc_abclkdiv;
363 if rising_edge(CLKS) then
365 report "serport_2clock2-W: RXOVR = " & slbit'image(RXOVR) &
366 "; data loss in receive fifo"
369 report "serport_2clock2-W: RXERR = " & slbit'image(RXERR) &
370 "; spurious receive error"
373 end process proc_check;
BUSY_WACK boolean := false
POUT_SINGLE boolean := false
out DO slv( DWIDTH- 1 downto 0)
in DI slv( DWIDTH- 1 downto 0)
slv8 :=( others => '0') UART_TXDATA
slv( RXFAWIDTH- 1 downto 0) :=( others => '0') RXFIFO_SIZEW
slv3 :=( others => '0') ABCLKDIV_F
slv8 :=( others => '0') TXFIFO_DO
slv( cd_range ) :=( others => '0') ABCLKDIV_U
slv( cd_range ) :=( others => '0') ABCLKDIV
slbit := '0' XONTX_TXBUSY
integer range CDWIDTH- 1 downto 0 cd_range
slv8 :=( others => '0') UART_RXDATA
slv3 :=( others => '0') ABCLKDIV_F_U
slv8 :=( others => '0') RXFIFO_DI
out MONI serport_moni_type
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2