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W11 CPU core and support modules
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tb_cmoda7_sram.vhd
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1-- $Id: tb_cmoda7_sram.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_cmoda7_sram - sim
7-- Description: Test bench for cmoda7 (base+sram)
8--
9-- Dependencies: simlib/simclk
10-- simlib/simclkcnt
11-- rlink/tbcore/tbcore_rlink
12-- xlib/sfs_gsim_core
13-- tb_cmoda7_core
14-- serport/tb/serport_master_tb
15-- cmoda7_sram_aif [UUT]
16-- simlib/simbididly
17-- bplib/issi/is61wv5128bll
18--
19-- To test: generic, any cmoda7_sram_aif target
20--
21-- Target Devices: generic
22-- Tool versions: viv 2016.4-2018.2; ghdl 0.34
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2018-11-03 1064 1.0.1 use sfs_gsim_core
27-- 2017-06-04 906 1.0 Initial version (derived from tb_nexys4_cram)
28------------------------------------------------------------------------------
29
30library ieee;
31use ieee.std_logic_1164.all;
32use ieee.numeric_std.all;
33use ieee.std_logic_textio.all;
34use std.textio.all;
35
36use work.slvtypes.all;
37use work.rlinklib.all;
38use work.xlib.all;
39use work.cmoda7lib.all;
40use work.simlib.all;
41use work.simbus.all;
42use work.sys_conf.all;
43
46
47architecture sim of tb_cmoda7_sram is
48
49 signal CLKOSC : slbit := '0'; -- board clock (12 Mhz)
50 signal CLKCOM : slbit := '0'; -- communication clock
51
52 signal CLKCOM_CYCLE : integer := 0;
53
54 signal RESET : slbit := '0';
55 signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
56 signal RXDATA : slv8 := (others=>'0');
57 signal RXVAL : slbit := '0';
58 signal RXERR : slbit := '0';
59 signal RXACT : slbit := '0';
60 signal TXDATA : slv8 := (others=>'0');
61 signal TXENA : slbit := '0';
62 signal TXBUSY : slbit := '0';
63
64 signal I_RXD : slbit := '1';
65 signal O_TXD : slbit := '1';
66 signal I_BTN : slv2 := (others=>'0');
67 signal O_LED : slv2 := (others=>'0');
68 signal O_RGBLED0_N : slv3 := (others=>'0');
69
70 signal TB_MEM_CE_N : slbit := '1';
71 signal TB_MEM_WE_N : slbit := '1';
72 signal TB_MEM_OE_N : slbit := '1';
73 signal TB_MEM_ADDR : slv19 := (others=>'Z');
74 signal TB_MEM_DATA : slv8 := (others=>'0');
75
76 signal MM_MEM_CE_N : slbit := '1';
77 signal MM_MEM_WE_N : slbit := '1';
78 signal MM_MEM_OE_N : slbit := '1';
79 signal MM_MEM_ADDR : slv19 := (others=>'Z');
80 signal MM_MEM_DATA : slv8 := (others=>'0');
81
82 signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
83
84 constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
85
86 constant clock_period : Delay_length := 83.333 ns;
87 constant clock_offset : Delay_length := 2000 ns;
88 constant pcb_delay : Delay_length := 1 ns;
89
90begin
91
92 CLKGEN : simclk
93 generic map (
96 port map (
97 CLK => CLKOSC
98 );
99
100 CLKGEN_COM : sfs_gsim_core
101 generic map (
102 VCO_DIVIDE => sys_conf_clkser_vcodivide,
103 VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
104 OUT_DIVIDE => sys_conf_clkser_outdivide)
105 port map (
106 CLKIN => CLKOSC,
107 CLKFX => CLKCOM,
108 LOCKED => open
109 );
110
111 CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
112
113 TBCORE : entity work.tbcore_rlink
114 port map (
115 CLK => CLKCOM,
116 RX_DATA => TXDATA,
117 RX_VAL => TXENA,
118 RX_HOLD => TXBUSY,
119 TX_DATA => RXDATA,
120 TX_ENA => RXVAL
121 );
122
123 C7CORE : entity work.tb_cmoda7_core
124 port map (
125 I_BTN => I_BTN
126 );
127
128 UUT : cmoda7_sram_aif
129 port map (
130 I_CLK12 => CLKOSC,
131 I_RXD => I_RXD,
132 O_TXD => O_TXD,
133 I_BTN => I_BTN,
134 O_LED => O_LED,
135 O_RGBLED0_N => O_RGBLED0_N,
136 O_MEM_CE_N => TB_MEM_CE_N,
137 O_MEM_WE_N => TB_MEM_WE_N,
138 O_MEM_OE_N => TB_MEM_OE_N,
139 O_MEM_ADDR => TB_MEM_ADDR,
140 IO_MEM_DATA => TB_MEM_DATA
141 );
142
147
148 BUSDLY: simbididly
149 generic map (
150 DELAY => pcb_delay,
151 DWIDTH => 8)
152 port map (
153 A => TB_MEM_DATA,
155
156 MEM : entity work.is61wv5128bll
157 port map (
158 CE_N => MM_MEM_CE_N,
159 OE_N => MM_MEM_OE_N,
160 WE_N => MM_MEM_WE_N,
161 ADDR => MM_MEM_ADDR,
163 );
164
165 SERMSTR : entity work.serport_master_tb
166 generic map (
167 CDWIDTH => CLKDIV'length)
168 port map (
169 CLK => CLKCOM,
170 RESET => RESET,
171 CLKDIV => CLKDIV,
173 ENAESC => '0',
174 RXDATA => RXDATA,
175 RXVAL => RXVAL,
176 RXERR => RXERR,
177 RXOK => '1',
178 TXDATA => TXDATA,
179 TXENA => TXENA,
180 TXBUSY => TXBUSY,
181 RXSD => O_TXD,
182 TXSD => I_RXD,
183 RXRTS_N => open,
184 TXCTS_N => '0'
185 );
186
187 proc_moni: process
188 variable oline : line;
189 begin
190
191 loop
192 wait until rising_edge(CLKCOM);
193
194 if RXERR = '1' then
195 writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
196 writeline(output, oline);
197 end if;
198
199 end loop;
200
201 end process proc_moni;
202
203 --
204 -- Notes on portsel and XON control:
205 -- - most cmoda7 designs will use hardwired XON=1
206 -- - but some (especially basis tests) might not use flow control
207 -- - that's why XON flow control must be optional and configurable !
208 --
209 proc_simbus: process (SB_VAL)
210 begin
211 if SB_VAL'event and to_x01(SB_VAL)='1' then
212 if SB_ADDR = sbaddr_portsel then
213 R_PORTSEL_XON <= to_x01(SB_DATA(1));
214 end if;
215 end if;
216 end process proc_simbus;
217
218end sim;
inout DATA slv8
in ADDR slv19
in WE_N slbit
in CE_N slbit
in OE_N slbit
CDWIDTH positive := 13
in ENAESC slbit := '0'
in ENAXON slbit := '0'
in CLKDIV slv( CDWIDTH- 1 downto 0)
in RXOK slbit := '1'
in TXCTS_N slbit := '0'
VCO_DIVIDE positive := 1
OUT_DIVIDE positive := 1
in CLKIN slbit
VCO_MULTIPLY positive := 1
out LOCKED slbit
out CLKFX slbit
inout B slv( DWIDTH- 1 downto 0)
Definition: simbididly.vhd:32
inout A slv( DWIDTH- 1 downto 0)
Definition: simbididly.vhd:30
DELAY Delay_length
Definition: simbididly.vhd:27
DWIDTH positive := 16
Definition: simbididly.vhd:28
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
out CLK_CYCLE integer
Definition: simclkcnt.vhd:29
in CLK slbit
Definition: simclkcnt.vhd:27
std_logic_vector( 18 downto 0) slv19
Definition: slvtypes.vhd:52
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
slbit := '0' RXERR
slbit := '0' RESET
integer := 0 CLKCOM_CYCLE
slv2 := "00" CLKDIV
Delay_length := 83.333 ns clock_period
slbit := '0' TXENA
slv8 :=( others => '0') RXDATA
slbit := '1' MM_MEM_OE_N
Delay_length := 2000 ns clock_offset
slv19 :=( others => 'Z') MM_MEM_ADDR
slbit := '1' MM_MEM_CE_N
slbit := '1' TB_MEM_WE_N
slbit := '0' RXACT
slbit := '1' MM_MEM_WE_N
Delay_length := 1 ns pcb_delay
slv2 :=( others => '0') I_BTN
slbit := '0' RXVAL
slbit := '1' O_TXD
slv8 :=( others => '0') MM_MEM_DATA
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slbit := '0' CLKOSC
slbit := '1' TB_MEM_OE_N
slv3 :=( others => '0') O_RGBLED0_N
slbit := '0' CLKCOM
slbit := '0' TXBUSY
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TB_MEM_DATA
slv2 :=( others => '0') O_LED
slv8 :=( others => '0') TXDATA
slbit := '1' TB_MEM_CE_N
slbit := '1' I_RXD
slv19 :=( others => 'Z') TB_MEM_ADDR
Definition: xlib.vhd:35