31use ieee.std_logic_1164.
all;
32use ieee.numeric_std.
all;
33use ieee.std_logic_textio.
all;
128 UUT : cmoda7_sram_aif
188 variable oline : line;
192 wait until rising_edge(CLKCOM);
196 writeline(output, oline);
201 end process proc_moni;
209 proc_simbus:
process (SB_VAL)
211 if SB_VAL'event and to_x01(SB_VAL)='1' then
216 end process proc_simbus;
in CLKDIV slv( CDWIDTH- 1 downto 0)
VCO_MULTIPLY positive := 1
inout B slv( DWIDTH- 1 downto 0)
inout A slv( DWIDTH- 1 downto 0)
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 18 downto 0) slv19
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
integer := 0 CLKCOM_CYCLE
Delay_length := 83.333 ns clock_period
slv8 :=( others => '0') RXDATA
Delay_length := 2000 ns clock_offset
slv19 :=( others => 'Z') MM_MEM_ADDR
Delay_length := 1 ns pcb_delay
slv2 :=( others => '0') I_BTN
slv8 :=( others => '0') MM_MEM_DATA
slv8 := slv( to_unsigned( 8, 8) ) sbaddr_portsel
slv3 :=( others => '0') O_RGBLED0_N
slbit := '0' R_PORTSEL_XON
slv8 :=( others => '0') TB_MEM_DATA
slv2 :=( others => '0') O_LED
slv8 :=( others => '0') TXDATA
slv19 :=( others => 'Z') TB_MEM_ADDR