w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
tb_tst_serloop2_n3.vhd
Go to the documentation of this file.
1-- $Id: tb_tst_serloop2_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tb_tst_serloop2_n3 - sim
7-- Description: Test bench for sys_tst_serloop2_n3
8--
9-- Dependencies: simlib/simclk
10-- vlib/xlib/dcm_sfs
11-- sys_tst_serloop2_n3 [UUT]
12-- tb/tb_tst_serloop
13--
14-- To test: sys_tst_serloop2_n3
15--
16-- Target Devices: generic
17--
18-- Revision History:
19-- Date Rev Version Comment
20-- 2016-09-03 805 1.1 remove CLK_STOP logic (simstop via report)
21-- 2011-12-23 444 1.1 use new simclk
22-- 2011-12-11 438 1.0.1 temporarily use with ser=usr=100 MHz
23-- 2011-11-27 433 1.0 Initial version
24------------------------------------------------------------------------------
25
26library ieee;
27use ieee.std_logic_1164.all;
28use ieee.numeric_std.all;
29use ieee.std_logic_textio.all;
30use std.textio.all;
31
32use work.slvtypes.all;
33use work.xlib.all;
34use work.simlib.all;
35
38
39architecture sim of tb_tst_serloop2_n3 is
40
41 signal CLK100 : slbit := '0';
42
43 signal CLKS : slbit := '0';
44 signal CLKH : slbit := '0';
45
46 signal I_RXD : slbit := '1';
47 signal O_TXD : slbit := '1';
48 signal I_SWI : slv8 := (others=>'0');
49 signal I_BTN : slv5 := (others=>'0');
50
51 signal O_FUSP_RTS_N : slbit := '0';
52 signal I_FUSP_CTS_N : slbit := '0';
53 signal I_FUSP_RXD : slbit := '1';
54 signal O_FUSP_TXD : slbit := '1';
55
56 signal RXD : slbit := '1';
57 signal TXD : slbit := '1';
58 signal SWI : slv8 := (others=>'0');
59 signal BTN : slv5 := (others=>'0');
60
61 signal FUSP_RTS_N : slbit := '0';
62 signal FUSP_CTS_N : slbit := '0';
63 signal FUSP_RXD : slbit := '1';
64 signal FUSP_TXD : slbit := '1';
65
66 constant clock_period : Delay_length := 10 ns;
67 constant clock_offset : Delay_length := 200 ns;
68 constant delay_time : Delay_length := 2 ns;
69
70begin
71
72 SYSCLK : simclk
73 generic map (
76 port map (
77 CLK => CLK100
78 );
79
80 DCM_S : dcm_sfs
81 generic map (
82 CLKFX_DIVIDE => 1, -- currently 1-to-1
83 CLKFX_MULTIPLY => 1,
84 CLKIN_PERIOD => 10.0)
85 port map (
86 CLKIN => CLK100,
87 CLKFX => CLKS,
88 LOCKED => open
89 );
90
91 DCM_H : dcm_sfs
92 generic map (
93 CLKFX_DIVIDE => 1, -- currently 1-to-1
94 CLKFX_MULTIPLY => 1,
95 CLKIN_PERIOD => 10.0)
96 port map (
97 CLKIN => CLK100,
98 CLKFX => CLKH,
99 LOCKED => open
100 );
101
102 UUT : entity work.sys_tst_serloop2_n3
103 port map (
104 I_CLK100 => CLK100,
105 I_RXD => I_RXD,
106 O_TXD => O_TXD,
107 I_SWI => I_SWI,
108 I_BTN => I_BTN,
109 O_LED => open,
110 O_ANO_N => open,
111 O_SEG_N => open,
112 O_MEM_CE_N => open,
113 O_MEM_BE_N => open,
114 O_MEM_WE_N => open,
115 O_MEM_OE_N => open,
116 O_MEM_ADV_N => open,
117 O_MEM_CLK => open,
118 O_MEM_CRE => open,
119 I_MEM_WAIT => '0',
120 O_MEM_ADDR => open,
121 IO_MEM_DATA => open,
122 O_PPCM_CE_N => open,
123 O_PPCM_RST_N => open,
128 );
129
130 GENTB : entity work.tb_tst_serloop
131 port map (
132 CLKS => CLKS,
133 CLKH => CLKH,
134 P0_RXD => RXD,
135 P0_TXD => TXD,
136 P0_RTS_N => '0',
137 P0_CTS_N => open,
138 P1_RXD => FUSP_RXD,
139 P1_TXD => FUSP_TXD,
142 SWI => SWI,
143 BTN => BTN(3 downto 0)
144 );
145
146 I_RXD <= RXD after delay_time;
147 TXD <= O_TXD after delay_time;
152
153 I_SWI <= SWI after delay_time;
154 I_BTN <= BTN after delay_time;
155
156end sim;
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
out CLK slbit
Definition: simclk.vhd:33
OFFSET Delay_length := 200 ns
Definition: simclk.vhd:31
PERIOD Delay_length := 20 ns
Definition: simclk.vhd:30
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
Delay_length := 2 ns delay_time
Delay_length := 10 ns clock_period
slv8 :=( others => '0') SWI
Delay_length := 200 ns clock_offset
slv5 :=( others => '0') I_BTN
slv8 :=( others => '0') I_SWI
slv5 :=( others => '0') BTN
out P0_RXD slbit
in P1_RTS_N slbit
in P1_TXD slbit
in P0_TXD slbit
out P0_CTS_N slbit
out P1_RXD slbit
in P0_RTS_N slbit
out P1_CTS_N slbit
Definition: xlib.vhd:35