27use ieee.std_logic_1164.
all;
28use ieee.numeric_std.
all;
29use ieee.std_logic_textio.
all;
CLKFX_DIVIDE positive := 1
CLKFX_MULTIPLY positive := 1
CLKIN_PERIOD real := 20.0
OFFSET Delay_length := 200 ns
PERIOD Delay_length := 20 ns
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 7 downto 0) slv8
Delay_length := 2 ns delay_time
Delay_length := 10 ns clock_period
slv8 :=( others => '0') SWI
Delay_length := 200 ns clock_offset
slv5 :=( others => '0') I_BTN
slv8 :=( others => '0') I_SWI
slv5 :=( others => '0') BTN
slbit := '0' O_FUSP_RTS_N
slbit := '0' I_FUSP_CTS_N