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W11 CPU core and support modules
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sys_tst_serloop2_n3.vhd
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1-- $Id: sys_tst_serloop2_n3.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop2_n3 - syn
7-- Description: Serial link tester design for nexys3 (serport_2clock case)
8--
9-- Dependencies: vlib/xlib/dcm_sfs
10-- genlib/clkdivce
11-- bpgen/bp_rs232_2l4l_iob
12-- bpgen/sn_humanio
13-- tst_serloop_hiomap
14-- vlib/serport/serport_2clock
15-- tst_serloop
16-- vlib/nxcramlib/nx_cram_dummy
17--
18-- Test bench: -
19--
20-- Target Devices: generic
21-- Tool versions: xst 13.1; ghdl 0.29
22--
23-- Synthesized (xst):
24-- Date Rev ise Target flop lutl lutm slic t peri
25-- 2011-11-27 433 13.1 O40d xc6slx16-2 486 652 59 237 t 6.3
26--
27-- Revision History:
28-- Date Rev Version Comment
29-- 2011-12-11 438 1.0.2 add dcm monitor hack; use with ser=usr=100 MHz
30-- 2011-12-09 437 1.0.1 rename serport stat->moni port
31-- 2011-11-27 433 1.0 Initial version
32------------------------------------------------------------------------------
33--
34
35library ieee;
36use ieee.std_logic_1164.all;
37use ieee.numeric_std.all;
38
39use work.slvtypes.all;
40use work.xlib.all;
41use work.genlib.all;
42use work.bpgenlib.all;
43use work.tst_serlooplib.all;
44use work.serportlib.all;
45use work.nxcramlib.all;
46use work.sys_conf.all;
47
48-- ----------------------------------------------------------------------------
49
50entity sys_tst_serloop2_n3 is -- top level
51 -- implements nexys3_fusp_aif
52 port (
53 I_CLK100 : in slbit; -- 100 MHz clock
54 I_RXD : in slbit; -- receive data (board view)
55 O_TXD : out slbit; -- transmit data (board view)
56 I_SWI : in slv8; -- n3 switches
57 I_BTN : in slv5; -- n3 buttons
58 O_LED : out slv8; -- n3 leds
59 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
60 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
61 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
62 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
63 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
64 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
65 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
66 O_MEM_CLK : out slbit; -- cram: clock
67 O_MEM_CRE : out slbit; -- cram: command register enable
68 I_MEM_WAIT : in slbit; -- cram: mem wait
69 O_MEM_ADDR : out slv23; -- cram: address lines
70 IO_MEM_DATA : inout slv16; -- cram: data lines
71 O_PPCM_CE_N : out slbit; -- ppcm: ...
72 O_PPCM_RST_N : out slbit; -- ppcm: ...
73 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
74 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
75 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
76 O_FUSP_TXD : out slbit -- fusp: rs232 tx
77 );
79
80architecture syn of sys_tst_serloop2_n3 is
81
82 signal CLK : slbit := '0';
83 signal RESET : slbit := '0';
84
85 signal CE_USEC : slbit := '0';
86 signal CE_MSEC : slbit := '0';
87
88 signal CLKS : slbit := '0';
89 signal CES_MSEC : slbit := '0';
90
91 signal RXD : slbit := '0';
92 signal TXD : slbit := '0';
93 signal CTS_N : slbit := '0';
94 signal RTS_N : slbit := '0';
95
96 signal SWI : slv8 := (others=>'0');
97 signal BTN : slv5 := (others=>'0');
98 signal LED : slv8 := (others=>'0');
99 signal LED_OUT : slv8 := (others=>'0');
100 signal DSP_DAT : slv16 := (others=>'0');
101 signal DSP_DP : slv4 := (others=>'0');
102
103 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
104 signal HIO_STAT : hio_stat_type := hio_stat_init;
105
106 signal RXDATA : slv8 := (others=>'0');
107 signal RXVAL : slbit := '0';
108 signal RXHOLD : slbit := '0';
109 signal TXDATA : slv8 := (others=>'0');
110 signal TXENA : slbit := '0';
111 signal TXBUSY : slbit := '0';
112
113 signal SER_MONI : serport_moni_type := serport_moni_init;
114
115 -- some signals for dcm monitor hack
116 signal LOCKED_DCMU : slbit := '0';
117 signal LOCKED_DCMS : slbit := '0';
118 signal R_MSECU_CNT : slv10 := (others=>'0');
119 signal R_MSECS_CNT : slv10 := (others=>'0');
120
121begin
122
123 DCM_U : dcm_sfs
124 generic map (
125 CLKFX_DIVIDE => 1, -- was 2
126 CLKFX_MULTIPLY => 1, -- was 3
127 CLKIN_PERIOD => 10.0)
128 port map (
129 CLKIN => I_CLK100,
130 CLKFX => CLK,
132 );
133
134 CLKDIV_U : clkdivce
135 generic map (
136 CDUWIDTH => 8,
137 USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 150 sim: 30
138 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
139 port map (
140 CLK => CLK,
141 CE_USEC => open,
143 );
144
145 DCM_S : dcm_sfs
146 generic map (
147 CLKFX_DIVIDE => 1, -- was 5
148 CLKFX_MULTIPLY => 1, -- was 3
149 CLKIN_PERIOD => 10.0)
150 port map (
151 CLKIN => I_CLK100,
152 CLKFX => CLKS,
154 );
155
156 CLKDIV_S : clkdivce
157 generic map (
158 CDUWIDTH => 7,
159 USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
160 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
161 port map (
162 CLK => CLKS,
163 CE_USEC => open,
165 );
166
167 HIO : sn_humanio
168 generic map (
169 BWIDTH => 5,
170 DEBOUNCE => sys_conf_hio_debounce)
171 port map (
172 CLK => CLK,
173 RESET => '0',
174 CE_MSEC => CE_MSEC,
175 SWI => SWI,
176 BTN => BTN,
177 LED => LED_OUT,
178 DSP_DAT => DSP_DAT,
179 DSP_DP => DSP_DP,
180 I_SWI => I_SWI,
181 I_BTN => I_BTN,
182 O_LED => O_LED,
183 O_ANO_N => O_ANO_N,
185 );
186
187 RESET <= BTN(0); -- BTN(0) will reset tester !!
188
189 HIOMAP : tst_serloop_hiomap
190 port map (
191 CLK => CLK,
192 RESET => RESET,
196 SWI => SWI,
197 BTN => BTN(3 downto 0),
198 LED => LED,
199 DSP_DAT => DSP_DAT,
200 DSP_DP => DSP_DP
201 );
202
203 IOB_RS232 : bp_rs232_2l4l_iob
204 port map (
205 CLK => CLKS,
206 RESET => '0',
207 SEL => SWI(0), -- port selection
208 RXD => RXD,
209 TXD => TXD,
210 CTS_N => CTS_N,
211 RTS_N => RTS_N,
212 I_RXD0 => I_RXD,
213 O_TXD0 => O_TXD,
218 );
219
220 SERPORT : serport_2clock
221 generic map (
222 CDWIDTH => 15,
223 CDINIT => sys_conf_uart_cdinit,
224 RXFAWIDTH => 5,
225 TXFAWIDTH => 5)
226 port map (
227 CLKU => CLK,
228 RESET => RESET,
229 CLKS => CLKS,
231 ENAXON => HIO_CNTL.enaxon,
232 ENAESC => HIO_CNTL.enaesc,
233 RXDATA => RXDATA,
234 RXVAL => RXVAL,
235 RXHOLD => RXHOLD,
236 TXDATA => TXDATA,
237 TXENA => TXENA,
238 TXBUSY => TXBUSY,
239 MONI => SER_MONI,
240 RXSD => RXD,
241 TXSD => TXD,
242 RXRTS_N => RTS_N,
243 TXCTS_N => CTS_N
244 );
245
246 TESTER : tst_serloop
247 port map (
248 CLK => CLK,
249 RESET => RESET,
250 CE_MSEC => CE_MSEC,
254 RXDATA => RXDATA,
255 RXVAL => RXVAL,
256 RXHOLD => RXHOLD,
257 TXDATA => TXDATA,
258 TXENA => TXENA,
259 TXBUSY => TXBUSY
260 );
261
262 SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
263 port map (
264 O_MEM_CE_N => O_MEM_CE_N,
265 O_MEM_BE_N => O_MEM_BE_N,
266 O_MEM_WE_N => O_MEM_WE_N,
267 O_MEM_OE_N => O_MEM_OE_N,
268 O_MEM_ADV_N => O_MEM_ADV_N,
269 O_MEM_CLK => O_MEM_CLK,
270 O_MEM_CRE => O_MEM_CRE,
271 I_MEM_WAIT => I_MEM_WAIT,
272 O_MEM_ADDR => O_MEM_ADDR,
273 IO_MEM_DATA => IO_MEM_DATA
274 );
275
276 O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
277 O_PPCM_RST_N <= '1'; --
278
279 -- this is a hack to monitor the two dcm's
280
281 proc_msecu: process (CLK)
282 begin
283 if rising_edge(CLK) then
284 if CE_MSEC = '1' then
285 R_MSECU_CNT <= slv(unsigned(R_MSECU_CNT) + 1);
286 end if;
287 end if;
288 end process proc_msecu;
289
290 proc_msecs: process (CLKS)
291 begin
292 if rising_edge(CLKS) then
293 if CES_MSEC = '1' then
294 R_MSECS_CNT <= slv(unsigned(R_MSECS_CNT) + 1);
295 end if;
296 end if;
297 end process proc_msecs;
298
299 LED_OUT(7) <= R_MSECU_CNT(9) or (not LOCKED_DCMU);
300 LED_OUT(6) <= R_MSECS_CNT(9) or (not LOCKED_DCMS);
301 LED_OUT(5 downto 0) <= LED(5 downto 0);
302
303end syn;
in RESET slbit := '0'
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
CLKFX_DIVIDE positive := 1
in CLKIN slbit
CLKFX_MULTIPLY positive := 1
out LOCKED slbit
CLKIN_PERIOD real := 20.0
out CLKFX slbit
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
out TXBUSY slbit
in CES_MSEC slbit
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 9 downto 0) slv10
Definition: slvtypes.vhd:42
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
slv10 :=( others => '0') R_MSECS_CNT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv8 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv10 :=( others => '0') R_MSECU_CNT
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') LED_OUT
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38
Definition: xlib.vhd:35