36use ieee.std_logic_1164.
all;
37use ieee.numeric_std.
all;
113 signal SER_MONI : serport_moni_type := serport_moni_init;
137 USECDIV => sys_conf_clkudiv_usecdiv,
138 MSECDIV => sys_conf_clkdiv_msecdiv
)
159 USECDIV => sys_conf_clksdiv_usecdiv,
160 MSECDIV => sys_conf_clkdiv_msecdiv
)
223 CDINIT => sys_conf_uart_cdinit,
231 ENAXON => HIO_CNTL.enaxon,
232 ENAESC => HIO_CNTL.enaesc,
262 SRAM_PROT :
nx_cram_dummy -- connect CRAM
to protection dummy
283 if rising_edge(CLK) then
288 end process proc_msecu;
292 if rising_edge(CLKS) then
297 end process proc_msecs;
CLKFX_DIVIDE positive := 1
CLKFX_MULTIPLY positive := 1
CLKIN_PERIOD real := 20.0
out MONI serport_moni_type
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 9 downto 0) slv10
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
out O_LED slv( LWIDTH- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
slv10 :=( others => '0') R_MSECS_CNT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv8 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv10 :=( others => '0') R_MSECU_CNT
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') LED_OUT
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in SER_MONI serport_moni_type
out HIO_STAT hio_stat_type
in HIO_CNTL hio_cntl_type