w11 - vhd 0.794
W11 CPU core and support modules
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rlink_sp1c.vhd
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1-- $Id: rlink_sp1c.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: rlink_sp1c - syn
7-- Description: rlink_core8 + serport_1clock combo
8--
9-- Dependencies: rlink_core8
10-- serport/serport_1clock
11-- rbus/rbd_rbmon
12-- rbus/rb_sres_or_2
13--
14-- Test bench: -
15--
16-- Target Devices: generic
17-- Tool versions: ise 13.1-14.7; viv 2014.4-2019.1; ghdl 0.29-0.35
18--
19-- Synthesized (xst):
20-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
21-- 2015-05-02 672 14.7 131013 xc6slx16-2 495 671 56 255 s 8.8 - -
22-- 2011-12-09 437 13.1 O40d xc3s1000-4 337 733 64 469 s 9.8 - -
23--
24-- Revision History:
25-- Date Rev Version Comment
26-- 2019-06-02 1159 4.2.1 use rbaddr_ constants
27-- 2015-05-02 672 4.2 add rbd_rbmon (optional via generics)
28-- 2015-04-11 666 4.1 rename ENAESC->ESCFILL, rearrange XON handling
29-- 2014-08-28 588 4.0 use rlink v4 iface, 4 bit STAT
30-- 2011-12-09 437 1.0 Initial version
31------------------------------------------------------------------------------
32
33library ieee;
34use ieee.std_logic_1164.all;
35use ieee.numeric_std.all;
36
37use work.slvtypes.all;
38use work.rblib.all;
39use work.rbdlib.all;
40use work.rlinklib.all;
41use work.serportlib.all;
42
43entity rlink_sp1c is -- rlink_core8+serport_1clock combo
44 generic (
45 BTOWIDTH : positive := 5; -- rbus timeout counter width
46 RTAWIDTH : positive := 12; -- retransmit buffer address width
47 SYSID : slv32 := (others=>'0'); -- rlink system id
48 IFAWIDTH : natural := 5; -- input fifo address width (0=none)
49 OFAWIDTH : natural := 5; -- output fifo address width (0=none)
50 ENAPIN_RLMON : integer := -1; -- SB_CNTL for rlmon (-1=none)
51 ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
52 ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
53 CDWIDTH : positive := 13; -- clk divider width
54 CDINIT : natural := 15; -- clk divider initial/reset setting
55 RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
56 RBMON_RBADDR : slv16 := rbaddr_rbmon); -- rbmon: base addr
57 port (
58 CLK : in slbit; -- clock
59 CE_USEC : in slbit; -- 1 usec clock enable
60 CE_MSEC : in slbit; -- 1 msec clock enable
61 CE_INT : in slbit := '0'; -- rri ato time unit clock enable
62 RESET : in slbit; -- reset
63 ENAXON : in slbit; -- enable xon/xoff handling
64 ESCFILL : in slbit; -- enable fill escaping
65 RXSD : in slbit; -- receive serial data (board view)
66 TXSD : out slbit; -- transmit serial data (board view)
67 CTS_N : in slbit := '0'; -- clear to send (act.low, board view)
68 RTS_N : out slbit; -- request to send (act.low, board view)
69 RB_MREQ : out rb_mreq_type; -- rbus: request
70 RB_SRES : in rb_sres_type; -- rbus: response
71 RB_LAM : in slv16; -- rbus: look at me
72 RB_STAT : in slv4; -- rbus: status flags
73 RL_MONI : out rl_moni_type; -- rlink_core: monitor port
74 SER_MONI : out serport_moni_type -- serport: monitor port
75 );
76end entity rlink_sp1c;
77
78
79architecture syn of rlink_sp1c is
80
81 signal RLB_DI : slv8 := (others=>'0');
82 signal RLB_ENA : slbit := '0';
83 signal RLB_BUSY : slbit := '0';
84 signal RLB_DO : slv8 := (others=>'0');
85 signal RLB_VAL : slbit := '0';
86 signal RLB_HOLD : slbit := '0';
87
88 signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
89 signal RB_SRES_M : rb_sres_type := rb_sres_init;
90 signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
91
92begin
93
94 CORE : rlink_core8 -- rlink master ----------------------
95 generic map (
96 BTOWIDTH => BTOWIDTH,
97 RTAWIDTH => RTAWIDTH,
98 SYSID => SYSID,
99 ENAPIN_RLMON => ENAPIN_RLMON,
100 ENAPIN_RLBMON=> ENAPIN_RLBMON,
101 ENAPIN_RBMON => ENAPIN_RBMON)
102 port map (
103 CLK => CLK,
104 CE_INT => CE_INT,
105 RESET => RESET,
106 ESCXON => ENAXON,
107 ESCFILL => ESCFILL,
108 RLB_DI => RLB_DI,
109 RLB_ENA => RLB_ENA,
110 RLB_BUSY => RLB_BUSY,
111 RLB_DO => RLB_DO,
112 RLB_VAL => RLB_VAL,
113 RLB_HOLD => RLB_HOLD,
114 RL_MONI => RL_MONI,
115 RB_MREQ => RB_MREQ_M,
116 RB_SRES => RB_SRES_M,
117 RB_LAM => RB_LAM,
118 RB_STAT => RB_STAT
119 );
120
121 SERPORT : serport_1clock -- serport interface -----------------
122 generic map (
123 CDWIDTH => CDWIDTH,
124 CDINIT => CDINIT,
125 RXFAWIDTH => IFAWIDTH,
126 TXFAWIDTH => OFAWIDTH)
127 port map (
128 CLK => CLK,
129 CE_MSEC => CE_MSEC,
130 RESET => RESET,
131 ENAXON => ENAXON,
132 ENAESC => '0', -- escaping now in rlink_core8
133 RXDATA => RLB_DI,
134 RXVAL => RLB_ENA,
135 RXHOLD => RLB_BUSY,
136 TXDATA => RLB_DO,
137 TXENA => RLB_VAL,
138 TXBUSY => RLB_HOLD,
139 MONI => SER_MONI,
140 RXSD => RXSD,
141 TXSD => TXSD,
142 RXRTS_N => RTS_N,
143 TXCTS_N => CTS_N
144 );
145
146 RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
147 begin
148 I0 : rbd_rbmon
149 generic map (
152 port map (
153 CLK => CLK,
154 RESET => RESET,
158 );
159 end generate RBMON;
160
161 RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
162 port map (
163 RB_SRES_1 => RB_SRES,
164 RB_SRES_2 => RB_SRES_RBMON,
165 RB_SRES_OR => RB_SRES_M
166 );
167
168 RB_MREQ <= RB_MREQ_M; -- setup output signals
169
170end syn;
in RESET slbit
Definition: rbd_rbmon.vhd:98
RB_ADDR slv16 := rbaddr_rbmon
Definition: rbd_rbmon.vhd:94
AWIDTH natural := 9
Definition: rbd_rbmon.vhd:95
in CLK slbit
Definition: rbd_rbmon.vhd:97
in RB_MREQ rb_mreq_type
Definition: rbd_rbmon.vhd:99
out RB_SRES rb_sres_type
Definition: rbd_rbmon.vhd:100
in RB_SRES_SUM rb_sres_type
Definition: rbd_rbmon.vhd:102
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40