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W11 CPU core and support modules
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sys_tst_serloop1_n4.vhd
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1-- $Id: sys_tst_serloop1_n4.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop1_n4 - syn
7-- Description: Serial link tester design for nexys4 (serport_1clock case)
8--
9-- Dependencies: vlib/xlib/s7_cmt_sfs
10-- vlib/genlib/clkdivce
11-- bpgen/bp_rs232_4line_iob
12-- bpgen/sn_humanio
13-- tst_serloop_hiomap
14-- vlib/serport/serport_1clock
15-- tst_serloop
16--
17-- Test bench: -
18--
19-- Target Devices: generic
20-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
21--
22-- Synthesized:
23-- Date Rev viv Target flop lutl lutm bram slic
24-- 2019-02-02 1108 2018.3 xc7a100t-1 409 454 16 0 190
25-- 2019-02-02 1108 2017.2 xc7a100t-1 409 445 16 0 189
26-- 2016-03-25 751 2015.4 xc7a100t-1 415 402 32 0 185
27--
28-- Revision History:
29-- Date Rev Version Comment
30-- 2016-06-05 772 1.1.1 use CDUWIDTH=7, 120 MHz clock is natural choice
31-- 2016-03-27 753 1.1 clock now from cmt and configurable
32-- 2015-02-06 643 1.1 factor out memory
33-- 2015-02-01 641 1.0 Initial version (derived from sys_tst_serloop1_n3)
34------------------------------------------------------------------------------
35--
36
37library ieee;
38use ieee.std_logic_1164.all;
39use ieee.numeric_std.all;
40
41use work.slvtypes.all;
42use work.xlib.all;
43use work.genlib.all;
44use work.bpgenlib.all;
45use work.tst_serlooplib.all;
46use work.serportlib.all;
47use work.sys_conf.all;
48
49-- ----------------------------------------------------------------------------
50
51entity sys_tst_serloop1_n4 is -- top level
52 -- implements nexys4_aif
53 port (
54 I_CLK100 : in slbit; -- 100 MHz clock
55 I_RXD : in slbit; -- receive data (board view)
56 O_TXD : out slbit; -- transmit data (board view)
57 O_RTS_N : out slbit; -- rx rts (board view; act.low)
58 I_CTS_N : in slbit; -- tx cts (board view; act.low)
59 I_SWI : in slv16; -- n4 switches
60 I_BTN : in slv5; -- n4 buttons
61 I_BTNRST_N : in slbit; -- n4 reset button
62 O_LED : out slv16; -- n4 leds
63 O_RGBLED0 : out slv3; -- n4 rgb-led 0
64 O_RGBLED1 : out slv3; -- n4 rgb-led 1
65 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
66 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
67 );
69
70architecture syn of sys_tst_serloop1_n4 is
71
72 signal CLK : slbit := '0';
73 signal RESET : slbit := '0';
74
75 signal CE_USEC : slbit := '0';
76 signal CE_MSEC : slbit := '0';
77
78 signal RXD : slbit := '0';
79 signal TXD : slbit := '0';
80 signal CTS_N : slbit := '0';
81 signal RTS_N : slbit := '0';
82
83 signal SWI : slv16 := (others=>'0');
84 signal BTN : slv5 := (others=>'0');
85 signal LED : slv16 := (others=>'0');
86 signal DSP_DAT : slv32 := (others=>'0');
87 signal DSP_DP : slv8 := (others=>'0');
88
89 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
90 signal HIO_STAT : hio_stat_type := hio_stat_init;
91
92 signal RXDATA : slv8 := (others=>'0');
93 signal RXVAL : slbit := '0';
94 signal RXHOLD : slbit := '0';
95 signal TXDATA : slv8 := (others=>'0');
96 signal TXENA : slbit := '0';
97 signal TXBUSY : slbit := '0';
98
99 signal SER_MONI : serport_moni_type := serport_moni_init;
100
101begin
102
103 GEN_CLKSYS : s7_cmt_sfs -- clock generator -------------------
104 generic map (
105 VCO_DIVIDE => sys_conf_clksys_vcodivide,
106 VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
107 OUT_DIVIDE => sys_conf_clksys_outdivide,
108 CLKIN_PERIOD => 10.0,
109 CLKIN_JITTER => 0.01,
110 STARTUP_WAIT => false,
111 GEN_TYPE => sys_conf_clksys_gentype)
112 port map (
113 CLKIN => I_CLK100,
114 CLKFX => CLK,
115 LOCKED => open
116 );
117
118 CLKDIV : clkdivce
119 generic map (
120 CDUWIDTH => 7,
121 USECDIV => sys_conf_clksys_mhz,
122 MSECDIV => sys_conf_clkdiv_msecdiv)
123 port map (
124 CLK => CLK,
125 CE_USEC => open,
127 );
128
129 HIO : sn_humanio
130 generic map (
131 SWIDTH => 16,
132 BWIDTH => 5,
133 LWIDTH => 16,
134 DCWIDTH => 3,
135 DEBOUNCE => sys_conf_hio_debounce)
136 port map (
137 CLK => CLK,
138 RESET => '0',
139 CE_MSEC => CE_MSEC,
140 SWI => SWI,
141 BTN => BTN,
142 LED => LED,
143 DSP_DAT => DSP_DAT,
144 DSP_DP => DSP_DP,
145 I_SWI => I_SWI,
146 I_BTN => I_BTN,
147 O_LED => O_LED,
148 O_ANO_N => O_ANO_N,
150 );
151
152 RESET <= BTN(0); -- BTN(0) will reset tester !!
153
154 HIOMAP : tst_serloop_hiomap
155 port map (
156 CLK => CLK,
157 RESET => RESET,
161 SWI => SWI(7 downto 0),
162 BTN => BTN(3 downto 0),
163 LED => LED(7 downto 0),
164 DSP_DAT => DSP_DAT(15 downto 0),
165 DSP_DP => DSP_DP(3 downto 0)
166 );
167
168 IOB_RS232 : bp_rs232_4line_iob
169 port map (
170 CLK => CLK,
171 RXD => RXD,
172 TXD => TXD,
173 CTS_N => CTS_N,
174 RTS_N => RTS_N,
175 I_RXD => I_RXD,
176 O_TXD => O_TXD,
177 I_CTS_N => I_CTS_N,
179 );
180
181 SERPORT : serport_1clock
182 generic map (
183 CDWIDTH => 12,
184 CDINIT => sys_conf_uart_cdinit,
185 RXFAWIDTH => 5,
186 TXFAWIDTH => 5)
187 port map (
188 CLK => CLK,
189 CE_MSEC => CE_MSEC,
190 RESET => RESET,
191 ENAXON => HIO_CNTL.enaxon,
192 ENAESC => HIO_CNTL.enaesc,
193 RXDATA => RXDATA,
194 RXVAL => RXVAL,
195 RXHOLD => RXHOLD,
196 TXDATA => TXDATA,
197 TXENA => TXENA,
198 TXBUSY => TXBUSY,
199 MONI => SER_MONI,
200 RXSD => RXD,
201 TXSD => TXD,
202 RXRTS_N => RTS_N,
203 TXCTS_N => CTS_N
204 );
205
206 TESTER : tst_serloop
207 port map (
208 CLK => CLK,
209 RESET => RESET,
210 CE_MSEC => CE_MSEC,
214 RXDATA => RXDATA,
215 RXVAL => RXVAL,
216 RXHOLD => RXHOLD,
217 TXDATA => TXDATA,
218 TXENA => TXENA,
219 TXBUSY => TXBUSY
220 );
221
222 -- show autobauder clock divisor on msb of display
223 DSP_DAT(31 downto 20) <= SER_MONI.abclkdiv(11 downto 0);
224 DSP_DAT(19) <= '0';
225 DSP_DAT(18 downto 16) <= SER_MONI.abclkdiv_f;
226 DSP_DP(7 downto 4) <= "0010";
227
228 -- setup unused outputs in nexys4
229 O_RGBLED0 <= (others=>'0');
230 O_RGBLED1 <= (others=>not I_BTNRST_N);
231
232end syn;
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
in CE_MSEC slbit
out TXBUSY slbit
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
DCWIDTH positive := 2
Definition: sn_humanio.vhd:53
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv32 :=( others => '0') DSP_DAT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv16 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv16 :=( others => '0') LED
slv8 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38
Definition: xlib.vhd:35