32use ieee.std_logic_1164.
all;
33use ieee.numeric_std.
all;
77 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
78 signal HIO_STAT : hio_stat_type := hio_stat_init;
87 signal SER_MONI : serport_moni_type := serport_moni_init;
91 GEN_CLKALL :
s7_cmt_1ce1ce -- clock generator system ------------
95 STARTUP_WAIT => false,
96 CLK0_VCODIV => sys_conf_clksys_vcodivide,
97 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
98 CLK0_OUTDIV => sys_conf_clksys_outdivide,
99 CLK0_GENTYPE => sys_conf_clksys_gentype,
101 CLK0_USECDIV => sys_conf_clksys_mhz,
102 CLK0_MSECDIV => sys_conf_clksys_msecdiv,
103 CLK1_VCODIV => sys_conf_clkser_vcodivide,
104 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
105 CLK1_OUTDIV => sys_conf_clkser_outdivide,
106 CLK1_GENTYPE => sys_conf_clkser_gentype,
108 CLK1_USECDIV => sys_conf_clkser_mhz,
109 CLK1_MSECDIV => sys_conf_clkser_msecdiv
)
171 CDINIT => sys_conf_uart_cdinit,
179 ENAXON => HIO_CNTL.enaxon,
180 ENAESC => HIO_CNTL.enaesc,
out MONI serport_moni_type
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
out O_LED slv( LWIDTH- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv16 :=( others => '0') DSP_DAT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv16 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv16 :=( others => '0') LED
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in SER_MONI serport_moni_type
out HIO_STAT hio_stat_type
in HIO_CNTL hio_cntl_type