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W11 CPU core and support modules
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sys_tst_serloop2_b3.vhd
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1-- $Id: sys_tst_serloop2_b3.vhd 1369 2023-02-08 18:59:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_serloop2_b3 - syn
7-- Description: Serial link tester design for basys3 (serport_2clock case)
8--
9-- Dependencies: bpgen/s7_cmt_1ce1ce
10-- bpgen/bp_rs232_2line_iob
11-- bpgen/sn_humanio
12-- tst_serloop_hiomap
13-- vlib/serport/serport_2clock2
14-- tst_serloop
15--
16-- Test bench: -
17--
18-- Target Devices: generic
19-- Tool versions: viv 2022.1; ghdl 2.0.0
20--
21-- Synthesized (viv):
22-- Date Rev viv Target flop lutl lutm bram slic
23-- 2023-02-07 1369 2022.1 xc7a35t-1 533 472 12 0.0 228
24--
25-- Revision History:
26-- Date Rev Version Comment
27-- 2023-02-07 1369 1.0 Initial version (derived from sys_tst_serloop1_b3)
28------------------------------------------------------------------------------
29--
30
31library ieee;
32use ieee.std_logic_1164.all;
33use ieee.numeric_std.all;
34
35use work.slvtypes.all;
36use work.bpgenlib.all;
37use work.tst_serlooplib.all;
38use work.serportlib.all;
39use work.sys_conf.all;
40
41-- ----------------------------------------------------------------------------
42
43entity sys_tst_serloop2_b3 is -- top level
44 -- implements basys3_aif
45 port (
46 I_CLK100 : in slbit; -- 100 MHz clock
47 I_RXD : in slbit; -- receive data (board view)
48 O_TXD : out slbit; -- transmit data (board view)
49 I_SWI : in slv16; -- b3 switches
50 I_BTN : in slv5; -- b3 buttons
51 O_LED : out slv16; -- b3 leds
52 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
53 O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
54 );
56
57architecture syn of sys_tst_serloop2_b3 is
58
59 signal CLK : slbit := '0';
60 signal RESET : slbit := '0';
61
62 signal CE_USEC : slbit := '0';
63 signal CE_MSEC : slbit := '0';
64
65 signal CLKS : slbit := '0';
66 signal CES_MSEC : slbit := '0';
67
68 signal RXD : slbit := '0';
69 signal TXD : slbit := '0';
70
71 signal SWI : slv16 := (others=>'0');
72 signal BTN : slv5 := (others=>'0');
73 signal LED : slv16 := (others=>'0');
74 signal DSP_DAT : slv16 := (others=>'0');
75 signal DSP_DP : slv4 := (others=>'0');
76
77 signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
78 signal HIO_STAT : hio_stat_type := hio_stat_init;
79
80 signal RXDATA : slv8 := (others=>'0');
81 signal RXVAL : slbit := '0';
82 signal RXHOLD : slbit := '0';
83 signal TXDATA : slv8 := (others=>'0');
84 signal TXENA : slbit := '0';
85 signal TXBUSY : slbit := '0';
86
87 signal SER_MONI : serport_moni_type := serport_moni_init;
88
89begin
90
91 GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
92 generic map (
93 CLKIN_PERIOD => 10.0,
94 CLKIN_JITTER => 0.01,
95 STARTUP_WAIT => false,
96 CLK0_VCODIV => sys_conf_clksys_vcodivide,
97 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
98 CLK0_OUTDIV => sys_conf_clksys_outdivide,
99 CLK0_GENTYPE => sys_conf_clksys_gentype,
100 CLK0_CDUWIDTH => 8,
101 CLK0_USECDIV => sys_conf_clksys_mhz,
102 CLK0_MSECDIV => sys_conf_clksys_msecdiv,
103 CLK1_VCODIV => sys_conf_clkser_vcodivide,
104 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
105 CLK1_OUTDIV => sys_conf_clkser_outdivide,
106 CLK1_GENTYPE => sys_conf_clkser_gentype,
107 CLK1_CDUWIDTH => 7,
108 CLK1_USECDIV => sys_conf_clkser_mhz,
109 CLK1_MSECDIV => sys_conf_clkser_msecdiv)
110 port map (
111 CLKIN => I_CLK100,
112 CLK0 => CLK,
113 CE0_USEC => CE_USEC,
114 CE0_MSEC => CE_MSEC,
115 CLK1 => CLKS,
116 CE1_USEC => open,
117 CE1_MSEC => CES_MSEC,
118 LOCKED => open
119 );
120
121 HIO : sn_humanio
122 generic map (
123 SWIDTH => 16,
124 BWIDTH => 5,
125 LWIDTH => 16,
126 DEBOUNCE => sys_conf_hio_debounce)
127 port map (
128 CLK => CLK,
129 RESET => '0',
130 CE_MSEC => CE_MSEC,
131 SWI => SWI,
132 BTN => BTN,
133 LED => LED,
134 DSP_DAT => DSP_DAT,
135 DSP_DP => DSP_DP,
136 I_SWI => I_SWI,
137 I_BTN => I_BTN,
138 O_LED => O_LED,
139 O_ANO_N => O_ANO_N,
141 );
142
143 RESET <= BTN(0); -- BTN(0) will reset tester !!
144
145 HIOMAP : tst_serloop_hiomap
146 port map (
147 CLK => CLK,
148 RESET => RESET,
152 SWI => SWI(7 downto 0),
153 BTN => BTN(3 downto 0),
154 LED => LED(7 downto 0),
155 DSP_DAT => DSP_DAT,
156 DSP_DP => DSP_DP
157 );
158
159 IOB_RS232 : bp_rs232_2line_iob
160 port map (
161 CLK => CLKS,
162 RXD => RXD,
163 TXD => TXD,
164 I_RXD => I_RXD,
165 O_TXD => O_TXD
166 );
167
168 SERPORT : serport_2clock2
169 generic map (
170 CDWIDTH => 12,
171 CDINIT => sys_conf_uart_cdinit,
172 RXFAWIDTH => 5,
173 TXFAWIDTH => 5)
174 port map (
175 CLKU => CLK,
176 RESET => RESET,
177 CLKS => CLKS,
179 ENAXON => HIO_CNTL.enaxon,
180 ENAESC => HIO_CNTL.enaesc,
181 RXDATA => RXDATA,
182 RXVAL => RXVAL,
183 RXHOLD => RXHOLD,
184 TXDATA => TXDATA,
185 TXENA => TXENA,
186 TXBUSY => TXBUSY,
187 MONI => SER_MONI,
188 RXSD => RXD,
189 TXSD => TXD,
190 RXRTS_N => open,
191 TXCTS_N => '0'
192 );
193
194 TESTER : tst_serloop
195 port map (
196 CLK => CLK,
197 RESET => RESET,
198 CE_MSEC => CE_MSEC,
202 RXDATA => RXDATA,
203 RXVAL => RXVAL,
204 RXHOLD => RXHOLD,
205 TXDATA => TXDATA,
206 TXENA => TXENA,
207 TXBUSY => TXBUSY
208 );
209
210end syn;
TXFAWIDTH natural := 5
CDWIDTH positive := 13
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
DEBOUNCE boolean := true
Definition: sn_humanio.vhd:54
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv16 :=( others => '0') DSP_DAT
hio_cntl_type := hio_cntl_init HIO_CNTL
slv16 :=( others => '0') SWI
serport_moni_type := serport_moni_init SER_MONI
slv8 :=( others => '0') RXDATA
hio_stat_type := hio_stat_init HIO_STAT
slv16 :=( others => '0') LED
slv4 :=( others => '0') DSP_DP
slv5 :=( others => '0') BTN
slv8 :=( others => '0') TXDATA
in HIO_STAT hio_stat_type
in SER_MONI serport_moni_type
out HIO_CNTL hio_cntl_type
in TXBUSY slbit
Definition: tst_serloop.vhd:48
in RESET slbit
Definition: tst_serloop.vhd:37
in RXDATA slv8
Definition: tst_serloop.vhd:42
in SER_MONI serport_moni_type
Definition: tst_serloop.vhd:41
out TXDATA slv8
Definition: tst_serloop.vhd:45
in CLK slbit
Definition: tst_serloop.vhd:36
out HIO_STAT hio_stat_type
Definition: tst_serloop.vhd:40
out RXHOLD slbit
Definition: tst_serloop.vhd:44
in RXVAL slbit
Definition: tst_serloop.vhd:43
in HIO_CNTL hio_cntl_type
Definition: tst_serloop.vhd:39
out TXENA slbit
Definition: tst_serloop.vhd:46
in CE_MSEC slbit
Definition: tst_serloop.vhd:38