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W11 CPU core and support modules
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sys_tst_sram_n4.vhd
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1-- $Id: sys_tst_sram_n4.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_sram_n4 - syn
7-- Description: test of nexys4 sram and its controller
8--
9-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce
10-- bplib/bpgen/bp_rs232_4line_iob
11-- bplib/bpgen/sn_humanio
12-- vlib/rlink/rlink_sp2c
13-- tst_sram
14-- bplib/nxcramlib/nx_cram_memctl_as
15-- bplib/sysmon/sysmonx_rbus_base
16-- vlib/rbus/rbd_usracc
17-- vlib/rbus/rb_sres_or_3
18--
19-- Test bench: tb/tb_tst_sram_n4
20--
21-- Target Devices: generic
22-- Tool versions: viv 2014.4-2018.3; ghdl 0.29-0.35 (ise 14.5-14.7 retired)
23--
24-- Synthesized:
25-- Date Rev viv Target flop lutl lutm bram slic
26-- 2019-02-02 1108 2018.3 xc7a100t-1 1042 1550 24 5 530
27-- 2019-02-02 1108 2017.2 xc7a100t-1 1043 1642 24 5 564
28-- 2017-01-14 844 2016.4 xc7a100t-1 1042 1677 24 5 557 +sysmon
29-- 2016-03-29 756 2015.4 xc7a100t-1 918 1207 24 5 428
30--
31-- Revision History:
32-- Date Rev Version Comment
33-- 2018-12-16 1086 1.7 use s7_cmt_1ce1ce
34-- 2017-01-14 844 1.6 add sysmon_rbus
35-- 2016-07-10 785 1.5.1 SWI(1) now XON
36-- 2016-07-09 784 1.5 tst_sram with AWIDTH and 22bit support
37-- 2016-04-02 758 1.4.1 add rbd_usracc (bitfile+jtag timestamp access)
38-- 2016-03-28 755 1.4 use serport_2clock2
39-- 2016-03-19 748 1.3.3 define rlink SYSID
40-- 2015-04-11 666 1.3.2 rearrange XON handling
41-- 2015-02-01 641 1.3.1 separate I_BTNRST_N
42-- 2015-01-31 640 1.3 drop fusp iface; use new sn_hio
43-- 2014-08-28 588 1.2 use new rlink v4 ifaceand 4 bit STAT
44-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
45-- 2013-09-28 535 1.0.1 use proper clock manager
46-- 2013-09-21 534 1.0 Initial version (derived from sys_tst_sram_n3)
47------------------------------------------------------------------------------
48
49library ieee;
50use ieee.std_logic_1164.all;
51use ieee.numeric_std.all;
52
53use work.slvtypes.all;
54use work.serportlib.all;
55use work.rblib.all;
56use work.rbdlib.all;
57use work.rlinklib.all;
58use work.bpgenlib.all;
59use work.sysmonrbuslib.all;
60use work.s3boardlib.all;
61use work.nxcramlib.all;
62use work.sys_conf.all;
63
64-- ----------------------------------------------------------------------------
65
66entity sys_tst_sram_n4 is -- top level
67 -- implements nexys4_cram_aif
68 port (
69 I_CLK100 : in slbit; -- 100 MHz clock
70 I_RXD : in slbit; -- receive data (board view)
71 O_TXD : out slbit; -- transmit data (board view)
72 O_RTS_N : out slbit; -- rx rts (board view; act.low)
73 I_CTS_N : in slbit; -- tx cts (board view; act.low)
74 I_SWI : in slv16; -- n4 switches
75 I_BTN : in slv5; -- n4 buttons
76 I_BTNRST_N : in slbit; -- n4 reset button
77 O_LED : out slv16; -- n4 leds
78 O_RGBLED0 : out slv3; -- n4 rgb-led 0
79 O_RGBLED1 : out slv3; -- n4 rgb-led 1
80 O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
81 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
82 O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
83 O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
84 O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
85 O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
86 O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
87 O_MEM_CLK : out slbit; -- cram: clock
88 O_MEM_CRE : out slbit; -- cram: command register enable
89 I_MEM_WAIT : in slbit; -- cram: mem wait
90 O_MEM_ADDR : out slv23; -- cram: address lines
91 IO_MEM_DATA : inout slv16 -- cram: data lines
92 );
94
95architecture syn of sys_tst_sram_n4 is
96
97 signal CLK : slbit := '0';
98
99 signal CE_USEC : slbit := '0';
100 signal CE_MSEC : slbit := '0';
101
102 signal CLKS : slbit := '0';
103 signal CES_MSEC : slbit := '0';
104
105 signal GBL_RESET : slbit := '0';
106
107 signal RXD : slbit := '1';
108 signal TXD : slbit := '0';
109 signal CTS_N : slbit := '0';
110 signal RTS_N : slbit := '0';
111
112 signal SWI : slv16 := (others=>'0');
113 signal BTN : slv5 := (others=>'0');
114 signal LED : slv16 := (others=>'0');
115 signal DSP_DAT : slv32 := (others=>'0');
116 signal DSP_DP : slv8 := (others=>'0');
117
118 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
119 signal RB_SRES : rb_sres_type := rb_sres_init;
120 signal RB_LAM : slv16 := (others=>'0');
121 signal RB_STAT : slv4 := (others=>'0');
122
123 signal SER_MONI : serport_moni_type := serport_moni_init;
124
125 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
126 signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
127 signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
128
129 signal RB_LAM_TST : slbit := '0';
130
131 signal MEM_RESET : slbit := '0';
132 signal MEM_REQ : slbit := '0';
133 signal MEM_WE : slbit := '0';
134 signal MEM_BUSY : slbit := '0';
135 signal MEM_ACK_R : slbit := '0';
136 signal MEM_ACK_W : slbit := '0';
137 signal MEM_ACT_R : slbit := '0';
138 signal MEM_ACT_W : slbit := '0';
139 signal MEM_ADDR : slv22 := (others=>'0');
140 signal MEM_BE : slv4 := (others=>'0');
141 signal MEM_DI : slv32 := (others=>'0');
142 signal MEM_DO : slv32 := (others=>'0');
143
144 constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
145
146 constant sysid_proj : slv16 := x"0104"; -- tst_sram
147 constant sysid_board : slv8 := x"05"; -- nexys4
148 constant sysid_vers : slv8 := x"00";
149
150begin
151
152 GEN_CLKALL : s7_cmt_1ce1ce -- clock generator system ------------
153 generic map (
154 CLKIN_PERIOD => 10.0,
155 CLKIN_JITTER => 0.01,
156 STARTUP_WAIT => false,
157 CLK0_VCODIV => sys_conf_clksys_vcodivide,
158 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
159 CLK0_OUTDIV => sys_conf_clksys_outdivide,
160 CLK0_GENTYPE => sys_conf_clksys_gentype,
161 CLK0_CDUWIDTH => 7,
162 CLK0_USECDIV => sys_conf_clksys_mhz,
163 CLK0_MSECDIV => 1000,
164 CLK1_VCODIV => sys_conf_clkser_vcodivide,
165 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
166 CLK1_OUTDIV => sys_conf_clkser_outdivide,
167 CLK1_GENTYPE => sys_conf_clkser_gentype,
168 CLK1_CDUWIDTH => 7,
169 CLK1_USECDIV => sys_conf_clkser_mhz,
170 CLK1_MSECDIV => 1000)
171 port map (
172 CLKIN => I_CLK100,
173 CLK0 => CLK,
174 CE0_USEC => CE_USEC,
175 CE0_MSEC => CE_MSEC,
176 CLK1 => CLKS,
177 CE1_USEC => open,
178 CE1_MSEC => CES_MSEC,
179 LOCKED => open
180 );
181
182 IOB_RS232 : bp_rs232_4line_iob
183 port map (
184 CLK => CLKS,
185 RXD => RXD,
186 TXD => TXD,
187 CTS_N => CTS_N,
188 RTS_N => RTS_N,
189 I_RXD => I_RXD,
190 O_TXD => O_TXD,
191 I_CTS_N => I_CTS_N,
193 );
194
195 HIO : sn_humanio
196 generic map (
197 SWIDTH => 16,
198 BWIDTH => 5,
199 LWIDTH => 16,
200 DCWIDTH => 3)
201 port map (
202 CLK => CLK,
203 RESET => '0',
204 CE_MSEC => CE_MSEC,
205 SWI => SWI,
206 BTN => BTN,
207 LED => LED,
208 DSP_DAT => DSP_DAT,
209 DSP_DP => DSP_DP,
210 I_SWI => I_SWI,
211 I_BTN => I_BTN,
212 O_LED => O_LED,
213 O_ANO_N => O_ANO_N,
215 );
216
217 RLINK : rlink_sp2c
218 generic map (
219 BTOWIDTH => 6, -- 64 cycles access timeout
220 RTAWIDTH => 12,
221 SYSID => sysid_proj & sysid_board & sysid_vers ,
222 IFAWIDTH => 5, -- 32 word input fifo
223 OFAWIDTH => 5, -- 32 word output fifo
224 ENAPIN_RLMON => sbcntl_sbf_rlmon,
225 ENAPIN_RBMON => sbcntl_sbf_rbmon,
226 CDWIDTH => 12,
227 CDINIT => sys_conf_ser2rri_cdinit,
228 RBMON_AWIDTH => 0,
229 RBMON_RBADDR => x"ffe8")
230 port map (
231 CLK => CLK,
232 CE_USEC => CE_USEC,
233 CE_MSEC => CE_MSEC,
234 CE_INT => CE_MSEC,
235 RESET => GBL_RESET,
236 CLKS => CLKS,
238 ENAXON => SWI(1),
239 ESCFILL => '0',
240 RXSD => RXD,
241 TXSD => TXD,
242 CTS_N => CTS_N,
243 RTS_N => RTS_N,
244 RB_MREQ => RB_MREQ,
245 RB_SRES => RB_SRES,
246 RB_LAM => RB_LAM,
247 RB_STAT => RB_STAT,
248 RL_MONI => open,
250 );
251
252 TST : entity work.tst_sram
253 generic map (
254 RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
255 AWIDTH => 22)
256 port map (
257 CLK => CLK,
258 RESET => GBL_RESET,
259 RB_MREQ => RB_MREQ,
261 RB_STAT => RB_STAT,
263 SWI => SWI(7 downto 0),
264 BTN => BTN(3 downto 0),
265 LED => LED(7 downto 0),
266 DSP_DAT => DSP_DAT(15 downto 0),
268 MEM_REQ => MEM_REQ,
269 MEM_WE => MEM_WE,
276 MEM_BE => MEM_BE,
277 MEM_DI => MEM_DI,
278 MEM_DO => MEM_DO
279 );
280
281 CRAMCTL : nx_cram_memctl_as
282 generic map (
283 READ0DELAY => sys_conf_memctl_read0delay,
284 READ1DELAY => sys_conf_memctl_read1delay,
285 WRITEDELAY => sys_conf_memctl_writedelay)
286 port map (
287 CLK => CLK,
288 RESET => MEM_RESET,
289 REQ => MEM_REQ,
290 WE => MEM_WE,
291 BUSY => MEM_BUSY,
292 ACK_R => MEM_ACK_R,
293 ACK_W => MEM_ACK_W,
294 ACT_R => MEM_ACT_R,
295 ACT_W => MEM_ACT_W,
296 ADDR => MEM_ADDR,
297 BE => MEM_BE,
298 DI => MEM_DI,
299 DO => MEM_DO,
310 );
311
312 SMRB : sysmonx_rbus_base
313 generic map ( -- use default INIT_ (Vccint=1.00)
314 CLK_MHZ => sys_conf_clksys_mhz,
316 port map (
317 CLK => CLK,
318 RESET => GBL_RESET,
319 RB_MREQ => RB_MREQ,
321 ALM => open,
322 OT => open,
323 TEMP => open
324 );
325
326 UARB : rbd_usracc
327 port map (
328 CLK => CLK,
329 RB_MREQ => RB_MREQ,
331 );
332
333 RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
334 port map (
335 RB_SRES_1 => RB_SRES_TST,
336 RB_SRES_2 => RB_SRES_SYSMON,
337 RB_SRES_3 => RB_SRES_USRACC,
338 RB_SRES_OR => RB_SRES
339 );
340
341 RB_LAM(0) <= RB_LAM_TST;
342
343 DSP_DP(3) <= not SER_MONI.txok;
344 DSP_DP(2) <= SER_MONI.txact;
345 DSP_DP(1) <= not SER_MONI.rxok;
346 DSP_DP(0) <= SER_MONI.rxact;
347
348 DSP_DP(7 downto 4) <= "0010";
349 DSP_DAT(31 downto 16) <= SER_MONI.abclkdiv(11 downto 0) &
350 '0' & SER_MONI.abclkdiv_f;
351
352 -- setup unused outputs in nexys4
353 O_RGBLED0 <= (others=>'0');
354 O_RGBLED1 <= (others=>not I_BTNRST_N);
355
356end syn;
357
READ0DELAY positive := 4
WRITEDELAY positive := 4
inout IO_MEM_DATA slv16
READ1DELAY positive := 2
in CLK slbit
Definition: rbd_usracc.vhd:40
in RB_MREQ rb_mreq_type
Definition: rbd_usracc.vhd:41
out RB_SRES rb_sres_type
Definition: rbd_usracc.vhd:43
Definition: rblib.vhd:32
std_logic_vector( 22 downto 0) slv23
Definition: slvtypes.vhd:56
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 4 downto 0) slv5
Definition: slvtypes.vhd:37
std_logic_vector( 2 downto 0) slv3
Definition: slvtypes.vhd:35
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic_vector( 21 downto 0) slv22
Definition: slvtypes.vhd:55
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
std_logic_vector slv
Definition: slvtypes.vhd:31
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:63
out O_LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:66
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:62
DCWIDTH positive := 2
Definition: sn_humanio.vhd:53
out SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:59
in I_BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:65
LWIDTH positive := 8
Definition: sn_humanio.vhd:52
in I_SWI slv( SWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:64
out O_SEG_N slv8
Definition: sn_humanio.vhd:69
SWIDTH positive := 8
Definition: sn_humanio.vhd:50
out BTN slv( BWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:60
in CLK slbit
Definition: sn_humanio.vhd:56
BWIDTH positive := 4
Definition: sn_humanio.vhd:51
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
Definition: sn_humanio.vhd:67
in LED slv( LWIDTH- 1 downto 0)
Definition: sn_humanio.vhd:61
in RESET slbit := '0'
Definition: sn_humanio.vhd:57
in CE_MSEC slbit
Definition: sn_humanio.vhd:58
slv22 :=( others => '0') MEM_ADDR
slv32 :=( others => '0') DSP_DAT
slv8 := x"05" sysid_board
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
slv8 := x"00" sysid_vers
rb_sres_type := rb_sres_init RB_SRES_TST
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
slv16 := x"0104" sysid_proj
in I_BTNRST_N slbit
out O_MEM_WE_N slbit
out O_MEM_CE_N slbit
in I_MEM_WAIT slbit
out O_MEM_OE_N slbit
out O_MEM_CLK slbit
out O_RTS_N slbit
out O_MEM_ADV_N slbit
out O_MEM_ADDR slv23
out O_MEM_BE_N slv2
inout IO_MEM_DATA slv16
out O_MEM_CRE slbit
CLK_MHZ integer := 250
RB_ADDR slv16 := x"fb00"
in RB_MREQ rb_mreq_type
out RB_SRES rb_sres_type
in RESET slbit := '0'
in MEM_BUSY slbit
Definition: tst_sram.vhd:182
out MEM_DI slv32
Definition: tst_sram.vhd:189
AWIDTH natural := 18
Definition: tst_sram.vhd:167
in RESET slbit
Definition: tst_sram.vhd:170
in MEM_ACK_W slbit
Definition: tst_sram.vhd:184
out MEM_RESET slbit
Definition: tst_sram.vhd:179
out RB_LAM slbit
Definition: tst_sram.vhd:174
in BTN slv4
Definition: tst_sram.vhd:176
out MEM_BE slv4
Definition: tst_sram.vhd:188
out RB_STAT slv4
Definition: tst_sram.vhd:173
in MEM_ACT_W slbit
Definition: tst_sram.vhd:186
in CLK slbit
Definition: tst_sram.vhd:169
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
Definition: tst_sram.vhd:166
out MEM_REQ slbit
Definition: tst_sram.vhd:180
in RB_MREQ rb_mreq_type
Definition: tst_sram.vhd:171
out MEM_ADDR slv( AWIDTH- 1 downto 0)
Definition: tst_sram.vhd:187
in MEM_ACT_R slbit
Definition: tst_sram.vhd:185
in MEM_ACK_R slbit
Definition: tst_sram.vhd:183
out RB_SRES rb_sres_type
Definition: tst_sram.vhd:172
in MEM_DO slv32
Definition: tst_sram.vhd:191
out MEM_WE slbit
Definition: tst_sram.vhd:181
out DSP_DAT slv16
Definition: tst_sram.vhd:178
out LED slv8
Definition: tst_sram.vhd:177
in SWI slv8
Definition: tst_sram.vhd:175