50use ieee.std_logic_1164.
all;
51use ieee.numeric_std.
all;
118 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
119 signal RB_SRES : rb_sres_type := rb_sres_init;
123 signal SER_MONI : serport_moni_type := serport_moni_init;
152 GEN_CLKALL :
s7_cmt_1ce1ce -- clock generator system ------------
154 CLKIN_PERIOD =>
10.0,
155 CLKIN_JITTER =>
0.01,
156 STARTUP_WAIT => false,
157 CLK0_VCODIV => sys_conf_clksys_vcodivide,
158 CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
159 CLK0_OUTDIV => sys_conf_clksys_outdivide,
160 CLK0_GENTYPE => sys_conf_clksys_gentype,
162 CLK0_USECDIV => sys_conf_clksys_mhz,
163 CLK0_MSECDIV =>
1000,
164 CLK1_VCODIV => sys_conf_clkser_vcodivide,
165 CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
166 CLK1_OUTDIV => sys_conf_clkser_outdivide,
167 CLK1_GENTYPE => sys_conf_clkser_gentype,
169 CLK1_USECDIV => sys_conf_clkser_mhz,
170 CLK1_MSECDIV =>
1000)
221 SYSID => sysid_proj & sysid_board & sysid_vers ,
227 CDINIT => sys_conf_ser2rri_cdinit,
254 RB_ADDR =>
slv(to_unsigned
(2#0000000000000000#,
16)),
314 CLK_MHZ => sys_conf_clksys_mhz,
333 RB_SRES_OR :
rb_sres_or_3 -- rbus
or ---------------------------
348 DSP_DP(7 downto 4) <= "0010";
ENAPIN_RBMON integer :=- 1
out SER_MONI serport_moni_type
ENAPIN_RLMON integer :=- 1
RBMON_RBADDR slv16 := rbaddr_rbmon
RBMON_AWIDTH natural := 0
SYSID slv32 :=( others => '0')
std_logic_vector( 22 downto 0) slv23
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 4 downto 0) slv5
std_logic_vector( 2 downto 0) slv3
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 21 downto 0) slv22
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
out O_LED slv( LWIDTH- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv22 :=( others => '0') MEM_ADDR
slv32 :=( others => '0') DSP_DAT
slv8 := x"05" sysid_board
slv16 :=( others => '0') SWI
slv4 :=( others => '0') RB_STAT
slv32 :=( others => '0') MEM_DI
rb_sres_type := rb_sres_init RB_SRES_SYSMON
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
slv32 :=( others => '0') MEM_DO
rb_sres_type := rb_sres_init RB_SRES
slv16 :=( others => '0') LED
rb_sres_type := rb_sres_init RB_SRES_TST
slv8 :=( others => '0') DSP_DP
slv16 := x"fb00" rbaddr_sysmon
rb_sres_type := rb_sres_init RB_SRES_USRACC
slv16 :=( others => '0') RB_LAM
slv4 :=( others => '0') MEM_BE
slv5 :=( others => '0') BTN
slv16 := x"0104" sysid_proj
RB_ADDR slv16 := slv( to_unsigned( 2#0000000000000000#, 16) )
out MEM_ADDR slv( AWIDTH- 1 downto 0)