w11 - vhd 0.794
W11 CPU core and support modules
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tst_rlink_cuff.vhd
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1-- $Id: tst_rlink_cuff.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2012-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: tst_rlink_cuff - syn
7-- Description: tester for rlink over cuff
8--
9-- Dependencies: vlib/rlink/rlink_core8
10-- vlib/rlink/rlink_rlbmux
11-- vlib/serport/serport_1clock
12-- ../tst_rlink/rbd_tst_rlink
13-- vlib/rbus/rb_sres_or_2
14-- vlib/genlib/led_pulse_stretch
15--
16-- Test bench: -
17--
18-- Target Devices: generic
19-- Tool versions: xst 13.3-14.7; ghdl 0.29-0.33
20--
21-- Revision History:
22-- Date Rev Version Comment
23-- 2016-03-19 748 1.2.1 define rlink SYSID
24-- 2015-04-11 666 1.2 rearrange XON handling
25-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
26-- 2013-01-02 467 1.0.1 use 64 usec led pulse width
27-- 2012-12-29 466 1.0 Initial version
28------------------------------------------------------------------------------
29
30library ieee;
31use ieee.std_logic_1164.all;
32use ieee.numeric_std.all;
33
34use work.slvtypes.all;
35use work.genlib.all;
36use work.rblib.all;
37use work.rlinklib.all;
38use work.serportlib.all;
39use work.fx2lib.all;
40use work.sys_conf.all;
41
42-- ----------------------------------------------------------------------------
43
44entity tst_rlink_cuff is -- tester for rlink over cuff
45 port (
46 CLK : in slbit; -- clock
47 RESET : in slbit; -- reset
48 CE_USEC : in slbit; -- usec pulse
49 CE_MSEC : in slbit; -- msec pulse
50 RB_MREQ_TOP : out rb_mreq_type; -- rbus: request
51 RB_SRES_TOP : in rb_sres_type; -- rbus: response from top level
52 SWI : in slv8; -- hio: switches
53 BTN : in slv4; -- hio: buttons
54 LED : out slv8; -- hio: leds
55 DSP_DAT : out slv16; -- hio: display data
56 DSP_DP : out slv4; -- hio: display decimal points
57 RXSD : in slbit; -- receive serial data (uart view)
58 TXSD : out slbit; -- transmit serial data (uart view)
59 RTS_N : out slbit; -- receive rts (uart view, act.low)
60 CTS_N : in slbit; -- transmit cts (uart view, act.low)
61 FX2_RXDATA : in slv8; -- fx2: receiver data out
62 FX2_RXVAL : in slbit; -- fx2: receiver data valid
63 FX2_RXHOLD : out slbit; -- fx2: receiver data hold
64 FX2_TXDATA : out slv8; -- fx2: transmit data in
65 FX2_TXENA : out slbit; -- fx2: transmit data enable
66 FX2_TXBUSY : in slbit; -- fx2: transmit busy
67 FX2_TX2DATA : out slv8; -- fx2: transmit 2 data in
68 FX2_TX2ENA : out slbit; -- fx2: transmit 2 data enable
69 FX2_TX2BUSY : in slbit; -- fx2: transmit 2 busy
70 FX2_MONI : in fx2ctl_moni_type -- fx2: fx2ctl monitor
71 );
73
74architecture syn of tst_rlink_cuff is
75
76 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
77 signal RB_SRES : rb_sres_type := rb_sres_init;
78 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
79
80 signal RB_LAM : slv16 := (others=>'0');
81 signal RB_STAT : slv4 := (others=>'0');
82
83 signal SER_MONI : serport_moni_type := serport_moni_init;
84 signal STAT : slv8 := (others=>'0');
85
86 signal RLB_DI : slv8 := (others=>'0');
87 signal RLB_ENA : slbit := '0';
88 signal RLB_BUSY : slbit := '0';
89 signal RLB_DO : slv8 := (others=>'0');
90 signal RLB_VAL : slbit := '0';
91 signal RLB_HOLD : slbit := '0';
92
93 signal SER_RXDATA : slv8 := (others=>'0');
94 signal SER_RXVAL : slbit := '0';
95 signal SER_RXHOLD : slbit := '0';
96 signal SER_TXDATA : slv8 := (others=>'0');
97 signal SER_TXENA : slbit := '0';
98 signal SER_TXBUSY : slbit := '0';
99
100 signal FX2_TX2ENA_L : slbit := '0';
101 signal FX2_TXENA_L : slbit := '0';
102
103 signal FX2_TX2ENA_LED : slbit := '0';
104 signal FX2_TXENA_LED : slbit := '0';
105 signal FX2_RXVAL_LED : slbit := '0';
106
107 signal R_LEDDIV : slv6 := (others=>'0'); -- clock divider for LED pulses
108 signal R_LEDCE : slbit := '0'; -- ce every 64 usec
109
110 constant sysid_proj : slv16 := x"0103"; -- tst_rlink_cuff
111 constant sysid_board : slv8 := x"00"; -- generic
112 constant sysid_vers : slv8 := x"00";
113
114begin
115
116 RLCORE : rlink_core8
117 generic map (
118 BTOWIDTH => 6,
119 RTAWIDTH => 12,
120 SYSID => sysid_proj & sysid_board & sysid_vers ,
121 ENAPIN_RLMON => sbcntl_sbf_rlmon,
122 ENAPIN_RBMON => sbcntl_sbf_rbmon)
123 port map (
124 CLK => CLK,
125 CE_INT => CE_MSEC,
126 RESET => RESET,
127 ESCXON => SWI(1),
128 ESCFILL => '0',
129 RLB_DI => RLB_DI,
130 RLB_ENA => RLB_ENA,
132 RLB_DO => RLB_DO,
133 RLB_VAL => RLB_VAL,
135 RL_MONI => open,
136 RB_MREQ => RB_MREQ,
137 RB_SRES => RB_SRES,
138 RB_LAM => RB_LAM,
140 );
141
142 RLBMUX : rlink_rlbmux
143 port map (
144 SEL => SWI(2),
145 RLB_DI => RLB_DI,
146 RLB_ENA => RLB_ENA,
148 RLB_DO => RLB_DO,
149 RLB_VAL => RLB_VAL,
163 );
164
165 SERPORT : serport_1clock
166 generic map (
167 CDWIDTH => 15,
168 CDINIT => sys_conf_ser2rri_cdinit,
169 RXFAWIDTH => 5,
170 TXFAWIDTH => 5)
171 port map (
172 CLK => CLK,
173 CE_MSEC => CE_MSEC,
174 RESET => RESET,
175 ENAXON => SWI(1),
176 ENAESC => '0', -- escaping now in rlink_core8
178 RXVAL => SER_RXVAL,
181 TXENA => SER_TXENA,
183 MONI => SER_MONI,
184 RXSD => RXSD,
185 TXSD => TXSD,
186 RXRTS_N => RTS_N,
187 TXCTS_N => CTS_N
188 );
189
190 RBDTST : entity work.rbd_tst_rlink
191 port map (
192 CLK => CLK,
193 RESET => RESET,
194 CE_USEC => CE_USEC,
195 RB_MREQ => RB_MREQ,
197 RB_LAM => RB_LAM,
198 RB_STAT => RB_STAT,
200 RXSD => RXSD,
201 RXACT => SER_MONI.rxact,
202 STAT => STAT
203 );
204
205 RB_SRES_OR1 : rb_sres_or_2
206 port map (
210 );
211
212 TX2ENA_PSTR : led_pulse_stretch
213 port map (
214 CLK => CLK,
215 CE_INT => R_LEDCE,
216 RESET => '0',
217 DIN => FX2_TX2ENA_L,
219 );
220 TXENA_PSTR : led_pulse_stretch
221 port map (
222 CLK => CLK,
223 CE_INT => R_LEDCE,
224 RESET => '0',
225 DIN => FX2_TXENA_L,
227 );
228 RXVAL_PSTR : led_pulse_stretch
229 port map (
230 CLK => CLK,
231 CE_INT => R_LEDCE,
232 RESET => '0',
233 DIN => FX2_RXVAL,
235 );
236
237 proc_clkdiv: process (CLK)
238 begin
239
240 if rising_edge(CLK) then
241 R_LEDCE <= '0';
242 if CE_USEC = '1' then
243 R_LEDDIV <= slv(unsigned(R_LEDDIV) - 1);
244 if unsigned(R_LEDDIV) = 0 then
245 R_LEDCE <= '1';
246 end if;
247 end if;
248 end if;
249
250 end process proc_clkdiv;
251
252 proc_hiomux : process (SWI, SER_MONI, STAT, FX2_TX2BUSY,
254 begin
255
256 DSP_DAT <= SER_MONI.abclkdiv;
257
258 LED(7) <= SER_MONI.abact;
259 LED(6 downto 2) <= (others=>'0');
260 LED(1) <= STAT(1);
261 LED(0) <= STAT(0);
262
263 if SWI(2) = '0' then
264 DSP_DP(3) <= not SER_MONI.txok;
265 DSP_DP(2) <= SER_MONI.txact;
266 DSP_DP(1) <= not SER_MONI.rxok;
267 DSP_DP(0) <= SER_MONI.rxact;
268 else
269 DSP_DP(3) <= FX2_TX2BUSY;
271 DSP_DP(1) <= FX2_TXENA_LED;
272 DSP_DP(0) <= FX2_RXVAL_LED;
273 end if;
274
275 end process proc_hiomux;
276
280
281end syn;
in RESET slbit := '0'
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
Definition: rblib.vhd:32
TXFAWIDTH natural := 5
CDWIDTH positive := 13
in ENAESC slbit
in ENAXON slbit
in TXCTS_N slbit
RXFAWIDTH natural := 5
CDINIT natural := 15
out RXRTS_N slbit
out MONI serport_moni_type
out RXDATA slv8
out RXVAL slbit
out TXSD slbit
in RXHOLD slbit
in CE_MSEC slbit
out TXBUSY slbit
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 5 downto 0) slv6
Definition: slvtypes.vhd:38
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector slv
Definition: slvtypes.vhd:31