56use ieee.std_logic_1164.
all;
113 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
114 signal RB_SRES : rb_sres_type := rb_sres_init;
121 signal SER_MONI : serport_moni_type := serport_moni_init;
132 assert (sys_conf_clksys mod 1000000) = 0
133 report "assert sys_conf_clksys on MHz grid"
142 USECDIV => sys_conf_clksys_mhz,
193 SYSID => sysid_proj & sysid_board & sysid_vers ,
199 CDINIT => sys_conf_ser2rri_cdinit,
233 RXACT => SER_MONI.rxact,
262 LED(6 downto 2) <= (others=>'0');
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
in RB_SRES_TOP rb_sres_type
ENAPIN_RBMON integer :=- 1
out SER_MONI serport_moni_type
ENAPIN_RLMON integer :=- 1
RBMON_RBADDR slv16 := rbaddr_rbmon
RBMON_AWIDTH natural := 0
SYSID slv32 :=( others => '0')
std_logic_vector( 3 downto 0) slv4
std_logic_vector( 17 downto 0) slv18
std_logic_vector( 31 downto 0) slv32
std_logic_vector( 15 downto 0) slv16
std_logic_vector( 7 downto 0) slv8
std_logic_vector( 1 downto 0) slv2
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
out O_LED slv( LWIDTH- 1 downto 0)
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
in LED slv( LWIDTH- 1 downto 0)
slv16 :=( others => '0') DSP_DAT
slv8 :=( others => '0') LED
slv16 := x"fef0" rbaddr_hio
slv8 := x"01" sysid_board
slv4 :=( others => '0') RB_STAT
slv8 :=( others => '0') SWI
rb_mreq_type := rb_mreq_init RB_MREQ
serport_moni_type := serport_moni_init SER_MONI
rb_sres_type := rb_sres_init RB_SRES
slv4 :=( others => '0') DSP_DP
rb_sres_type := rb_sres_init RB_SRES_TST
slv4 :=( others => '0') BTN
slv16 :=( others => '0') RB_LAM
rb_sres_type := rb_sres_init RB_SRES_HIO
slv8 :=( others => '0') STAT
slv16 := x"0101" sysid_proj