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W11 CPU core and support modules
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sys_tst_rlink_s3.vhd
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1-- $Id: sys_tst_rlink_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
2-- SPDX-License-Identifier: GPL-3.0-or-later
3-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
4--
5------------------------------------------------------------------------------
6-- Module Name: sys_tst_rlink_s3 - syn
7-- Description: rlink tester design for s3board
8--
9-- Dependencies: vlib/genlib/clkdivce
10-- bplib/bpgen/bp_rs232_2l4l_iob
11-- bplib/bpgen/sn_humanio_rbus
12-- vlib/rlink/rlink_sp1c
13-- rbd_tst_rlink
14-- vlib/rbus/rb_sres_or_2
15-- bplib/s3board/s3_sram_dummy
16--
17-- Test bench: tb/tb_tst_rlink_s3
18--
19-- Target Devices: generic
20-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.33
21--
22-- Synthesized (xst):
23-- Date Rev ise Target flop lutl lutm slic t peri
24-- 2016-03-12 743 14.7 131013 xc3s1000e-4 931 2078 128 1383
25-- 2014-12-20 614 14.7 131013 xc3s1000e-4 916 1973 128 1316 t 15.9
26-- 2011-12-22 442 13.1 O40d xc3s1000e-4 765 1672 96 1088 t 12.6
27--
28-- Revision History:
29-- Date Rev Version Comment
30-- 2016-03-19 748 1.2.2 define rlink SYSID
31-- 2015-04-11 666 1.2.1 rearrange XON handling
32-- 2014-11-09 603 1.2 use new rlink v4 iface and 4 bit STAT
33-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
34-- 2011-12-22 442 1.0 Initial version (derived from sys_tst_rlink_n2)
35------------------------------------------------------------------------------
36-- Usage of S3board switches, Buttons, LEDs:
37--
38-- SWI(7:2): no function (only connected to sn_humanio_rbus)
39-- SWI(1): 1 enable XON
40-- SWI(0): 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
41-- 1 -> Pmod B/top RS232 port /
42--
43-- LED(7): SER_MONI.abact
44-- LED(6:2): no function (only connected to sn_humanio_rbus)
45-- LED(1): timer 1 busy
46-- LED(0): timer 0 busy
47--
48-- DSP: SER_MONI.clkdiv (from auto bauder)
49-- DP(3): not SER_MONI.txok (shows tx back pressure)
50-- DP(2): SER_MONI.txact (shows tx activity)
51-- DP(1): not SER_MONI.rxok (shows rx back pressure)
52-- DP(0): SER_MONI.rxact (shows rx activity)
53--
54
55library ieee;
56use ieee.std_logic_1164.all;
57
58use work.slvtypes.all;
59use work.genlib.all;
60use work.serportlib.all;
61use work.rblib.all;
62use work.rlinklib.all;
63use work.bpgenlib.all;
64use work.bpgenrbuslib.all;
65use work.s3boardlib.all;
66use work.sys_conf.all;
67
68-- ----------------------------------------------------------------------------
69
70entity sys_tst_rlink_s3 is -- top level
71 -- implements s3board_fusp_aif
72 port (
73 I_CLK50 : in slbit; -- 50 MHz board clock
74 I_RXD : in slbit; -- receive data (board view)
75 O_TXD : out slbit; -- transmit data (board view)
76 I_SWI : in slv8; -- s3 switches
77 I_BTN : in slv4; -- s3 buttons
78 O_LED : out slv8; -- s3 leds
79 O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
80 O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
81 O_MEM_CE_N : out slv2; -- sram: chip enables (act.low)
82 O_MEM_BE_N : out slv4; -- sram: byte enables (act.low)
83 O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
84 O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
85 O_MEM_ADDR : out slv18; -- sram: address lines
86 IO_MEM_DATA : inout slv32; -- sram: data lines
87 O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
88 I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
89 I_FUSP_RXD : in slbit; -- fusp: rs232 rx
90 O_FUSP_TXD : out slbit -- fusp: rs232 tx
91 );
93
94architecture syn of sys_tst_rlink_s3 is
95
96 signal CLK : slbit := '0';
97
98 signal RXD : slbit := '1';
99 signal TXD : slbit := '0';
100 signal RTS_N : slbit := '0';
101 signal CTS_N : slbit := '0';
102
103 signal SWI : slv8 := (others=>'0');
104 signal BTN : slv4 := (others=>'0');
105 signal LED : slv8 := (others=>'0');
106 signal DSP_DAT : slv16 := (others=>'0');
107 signal DSP_DP : slv4 := (others=>'0');
108
109 signal RESET : slbit := '0';
110 signal CE_USEC : slbit := '0';
111 signal CE_MSEC : slbit := '0';
112
113 signal RB_MREQ : rb_mreq_type := rb_mreq_init;
114 signal RB_SRES : rb_sres_type := rb_sres_init;
115 signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
116 signal RB_SRES_TST : rb_sres_type := rb_sres_init;
117
118 signal RB_LAM : slv16 := (others=>'0');
119 signal RB_STAT : slv4 := (others=>'0');
120
121 signal SER_MONI : serport_moni_type := serport_moni_init;
122 signal STAT : slv8 := (others=>'0');
123
124 constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx
125
126 constant sysid_proj : slv16 := x"0101"; -- tst_rlink
127 constant sysid_board : slv8 := x"01"; -- s3board
128 constant sysid_vers : slv8 := x"00";
129
130begin
131
132 assert (sys_conf_clksys mod 1000000) = 0
133 report "assert sys_conf_clksys on MHz grid"
134 severity failure;
135
136 RESET <= '0'; -- so far not used
137 CLK <= I_CLK50;
138
139 CLKDIV : clkdivce
140 generic map (
141 CDUWIDTH => 7,
142 USECDIV => sys_conf_clksys_mhz,
143 MSECDIV => 1000)
144 port map (
145 CLK => CLK,
146 CE_USEC => CE_USEC,
148 );
149
150 IOB_RS232 : bp_rs232_2l4l_iob
151 port map (
152 CLK => CLK,
153 RESET => '0',
154 SEL => SWI(0),
155 RXD => RXD,
156 TXD => TXD,
157 CTS_N => CTS_N,
158 RTS_N => RTS_N,
159 I_RXD0 => I_RXD,
160 O_TXD0 => O_TXD,
165 );
166
167 HIO : sn_humanio_rbus
168 generic map (
169 DEBOUNCE => sys_conf_hio_debounce,
171 port map (
172 CLK => CLK,
173 RESET => RESET,
174 CE_MSEC => CE_MSEC,
175 RB_MREQ => RB_MREQ,
177 SWI => SWI,
178 BTN => BTN,
179 LED => LED,
180 DSP_DAT => DSP_DAT,
181 DSP_DP => DSP_DP,
182 I_SWI => I_SWI,
183 I_BTN => I_BTN,
184 O_LED => O_LED,
185 O_ANO_N => O_ANO_N,
187 );
188
189 RLINK : rlink_sp1c
190 generic map (
191 BTOWIDTH => 6,
192 RTAWIDTH => 12,
193 SYSID => sysid_proj & sysid_board & sysid_vers ,
194 IFAWIDTH => 5,
195 OFAWIDTH => 5,
196 ENAPIN_RLMON => sbcntl_sbf_rlmon,
197 ENAPIN_RBMON => sbcntl_sbf_rbmon,
198 CDWIDTH => 15,
199 CDINIT => sys_conf_ser2rri_cdinit,
200 RBMON_AWIDTH => 0, -- must be 0, rbmon in rbd_tst_rlink
201 RBMON_RBADDR => (others=>'0'))
202 port map (
203 CLK => CLK,
204 CE_USEC => CE_USEC,
205 CE_MSEC => CE_MSEC,
206 CE_INT => CE_MSEC,
207 RESET => RESET,
208 ENAXON => SWI(1),
209 ESCFILL => '0',
210 RXSD => RXD,
211 TXSD => TXD,
212 CTS_N => CTS_N,
213 RTS_N => RTS_N,
214 RB_MREQ => RB_MREQ,
215 RB_SRES => RB_SRES,
216 RB_LAM => RB_LAM,
217 RB_STAT => RB_STAT,
218 RL_MONI => open,
220 );
221
222 RBDTST : entity work.rbd_tst_rlink
223 port map (
224 CLK => CLK,
225 RESET => RESET,
226 CE_USEC => CE_USEC,
227 RB_MREQ => RB_MREQ,
229 RB_LAM => RB_LAM,
230 RB_STAT => RB_STAT,
232 RXSD => RXD,
233 RXACT => SER_MONI.rxact,
234 STAT => STAT
235 );
236
237 RB_SRES_OR1 : rb_sres_or_2
238 port map (
242 );
243
244 SRAM : s3_sram_dummy -- connect SRAM to protection dummy
245 port map (
246 O_MEM_CE_N => O_MEM_CE_N,
247 O_MEM_BE_N => O_MEM_BE_N,
248 O_MEM_WE_N => O_MEM_WE_N,
249 O_MEM_OE_N => O_MEM_OE_N,
250 O_MEM_ADDR => O_MEM_ADDR,
251 IO_MEM_DATA => IO_MEM_DATA
252 );
253
254 DSP_DAT <= SER_MONI.abclkdiv;
255
256 DSP_DP(3) <= not SER_MONI.txok;
257 DSP_DP(2) <= SER_MONI.txact;
258 DSP_DP(1) <= not SER_MONI.rxok;
259 DSP_DP(0) <= SER_MONI.rxact;
260
261 LED(7) <= SER_MONI.abact;
262 LED(6 downto 2) <= (others=>'0');
263 LED(1) <= STAT(1);
264 LED(0) <= STAT(0);
265
266end syn;
in RESET slbit := '0'
out CE_MSEC slbit
Definition: clkdivce.vhd:39
USECDIV positive := 50
Definition: clkdivce.vhd:33
CDUWIDTH positive := 6
Definition: clkdivce.vhd:32
out CE_USEC slbit
Definition: clkdivce.vhd:37
MSECDIV positive := 1000
Definition: clkdivce.vhd:34
in CLK slbit
Definition: clkdivce.vhd:36
in RB_SRES_2 rb_sres_type := rb_sres_init
out RB_SRES_OR rb_sres_type
in RB_SRES_1 rb_sres_type
Definition: rblib.vhd:32
std_logic_vector( 3 downto 0) slv4
Definition: slvtypes.vhd:36
std_logic_vector( 17 downto 0) slv18
Definition: slvtypes.vhd:51
std_logic_vector( 31 downto 0) slv32
Definition: slvtypes.vhd:59
std_logic_vector( 15 downto 0) slv16
Definition: slvtypes.vhd:48
std_logic slbit
Definition: slvtypes.vhd:30
std_logic_vector( 7 downto 0) slv8
Definition: slvtypes.vhd:40
std_logic_vector( 1 downto 0) slv2
Definition: slvtypes.vhd:34
in DSP_DP slv(( 2** DCWIDTH)- 1 downto 0)
DEBOUNCE boolean := true
out O_LED slv( LWIDTH- 1 downto 0)
RB_ADDR slv16 := x"fef0"
in DSP_DAT slv( 4*( 2** DCWIDTH)- 1 downto 0)
out SWI slv( SWIDTH- 1 downto 0)
in I_BTN slv( BWIDTH- 1 downto 0)
in I_SWI slv( SWIDTH- 1 downto 0)
out BTN slv( BWIDTH- 1 downto 0)
in RB_MREQ rb_mreq_type
out O_ANO_N slv(( 2** DCWIDTH)- 1 downto 0)
out RB_SRES rb_sres_type
in LED slv( LWIDTH- 1 downto 0)
in RESET slbit := '0'